Audio is in M4 domain, so we need an indepenent dts for audio.
M4 domain is controled by RTOS, this dts is for demo purpose in
linux
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
imx7ulp-14x14-arm2.dtb \
imx7ulp-evk.dtb \
imx7ulp-evk-emmc.dtb \
- imx7ulp-evk-lpuart.dtb
+ imx7ulp-evk-lpuart.dtb \
+ imx7ulp-evk-wm8960.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
--- /dev/null
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+/ {
+
+ aips0: aips-bus@41000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x41000000 0x80000>;
+ ranges;
+
+ pcc0: pcc0@41026000 {
+ compatible = "fsl,imx7ulp-pcc0";
+ reg = <0x41026000 0x1000>;
+ };
+
+ clks_m4: scg0@41027000 {
+ compatible = "fsl,imx7ulp-scg0";
+ reg = <0x41027000 0x1000>;
+ clocks = <&cm4_ckil>, <&cm4_osc>, <&cm4_sirc>, <&cm4_firc>;
+ clock-names = "cm4_ckil", "cm4_osc", "cm4_sirc", "cm4_firc";
+ #clock-cells = <1>;
+ };
+
+ sai0: sai@41037000 {
+ compatible = "fsl,imx7ulp-sai";
+ reg = <0x41037000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI0_IPG>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>,
+ <&clks_m4 IMX7ULP_CM4_CLK_SAI0_ROOT>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 0 59>, <&edma0 0 60>;
+ status = "disabled";
+ };
+ };
+
+ aips1: aips-bus@41080000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x41080000 0x80000>;
+ ranges;
+
+ smc0: smc0@410a4000 {
+ compatible = "fsl,imx7ulp-smc0";
+ reg = <0x410a4000 0x1000>;
+ };
+
+ sai1: sai@410AA000 {
+ compatible = "fsl,imx7ulp-sai";
+ reg = <0x410AA000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI1_IPG>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>,
+ <&clks_m4 IMX7ULP_CM4_CLK_SAI1_ROOT>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>,
+ <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 0 61>, <&edma0 0 62>;
+ status = "disabled";
+ };
+
+ pcc1: pcc1@410b2000 {
+ compatible = "fsl,imx7ulp-pcc1";
+ reg = <0x410b2000 0x1000>;
+ };
+ };
+
+ clocks_m4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cm4_ckil: clock@6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "cm4_ckil";
+ };
+
+ cm4_osc: clock@7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cm4_osc";
+ };
+
+ cm4_sirc: clock@8 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "cm4_sirc";
+ };
+
+ cm4_firc: clock@9 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "cm4_firc";
+ };
+ };
+
+
+ sound {
+ compatible = "fsl,imx7ulp-evk-wm8960",
+ "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ cpu-dai = <&sai0>;
+ audio-codec = <&codec>;
+ codec-master;
+ /* JD3: hp detect high for headphone*/
+ hp-det = <3 0>;
+ hp-det-gpios = <&gpio3 0 0>;
+ mic-det-gpios = <&gpio3 0 0>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "Mic Jack", "MICB";
+
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_0_1>;
+ status = "okay";
+
+ imx7ulp-evk-0 {
+ pinctrl_hog_0_1: hoggrp-0-1 {
+ fsl,pins = <
+ ULP1_PAD_PTA24__PTA24 0x127
+ ULP1_PAD_PTB0__CLKOUT 0x900
+ >;
+ };
+
+ pinctrl_sai0: sai0_grp {
+ fsl,pins = <
+ ULP1_PAD_PTA4__I2S0_MCLK 0x700
+ ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0700
+ ULP1_PAD_PTA2__I2S0_RXD0 0x0700
+ ULP1_PAD_PTA6__I2S0_TX_FS 0x0700
+ ULP1_PAD_PTA7__I2S0_TXD0 0x0700
+ >;
+ };
+ };
+};
+
+&iomuxc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_audio>;
+
+ imx7ulp-evk {
+ pinctrl_hog_audio: hoggrp-audio {
+ fsl,pins = <
+ ULP1_PAD_PTF0__PTF0 0x30100
+ >;
+ };
+ };
+};
+
+&lpi2c7 {
+ status = "okay";
+
+ codec: wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&clks_m4 IMX7ULP_CLK_SCG0_CLKOUT>;
+ clock-names = "mclk";
+ wlf,shared-lrclk;
+ assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_APLL_SEL>,
+ <&clks_m4 IMX7ULP_CLK_SCG0_CLKOUT>;
+ assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2>,
+ <&clks_m4 IMX7ULP_CM4_CLK_APLL_SEL>;
+ };
+};
+
+&clks_m4 {
+ assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL>,
+ <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO>,
+ <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1>,
+ <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2>,
+ <&clks_m4 IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV>;
+ assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_OSC>;
+ assigned-clock-rates = <0>, <540672000>, <49152000>, <12288000>, <270336000>;
+};
+
+&sai0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai0>;
+ assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI0_SEL>,
+ <&clks_m4 IMX7ULP_CM4_CLK_SAI0_DIV>;
+ assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV>;
+ assigned-clock-rates = <0>, <12288000>;
+ fsl,dataline = <0x1 0x1>;
+ status = "okay";
+};
>;
};
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <
+ ULP1_PAD_PTF12__LPI2C7_SCL 0x527
+ ULP1_PAD_PTF13__LPI2C7_SDA 0x527
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
ULP1_PAD_PTE3__SDHC1_CMD 0x843
};
};
+&lpi2c7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+};
+
&lpuart4 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart4>;
#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
-#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0xd1b8 0x7 0x2
+#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1
#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0
#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1
#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1
-#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0xd1bc 0x7 0x1
+#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1
#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0
#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0
#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1
#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1
#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1
#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1
-#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0xd1dc 0x7 0x1
+#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1
#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1
#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1
-#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0xd1e0 0x7 0x1
+#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1
#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0
#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0
#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1
#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1
#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1
#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1
-#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0xd1b4 0x7 0x1
+#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1
#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0
#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0
#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1
#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0
#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1
#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1
-#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0xd1c0 0x7 0x1
+#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1
#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0
#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0
#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1
#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1
#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1
#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1
-#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0xd1c4 0x7 0x1
+#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1
#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0
#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0
#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1
#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1
#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1
#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1
-#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0xd1b8 0x7 0x1
+#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1
#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0
#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0
#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1
#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1
-#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0xd1bc 0x7 0x2
+#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2
#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0
#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0
#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1
#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1
#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1
#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1
-#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0xd1dc 0x7 0x2
+#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2
#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2
#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1
-#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0xd1e0 0x7 0x2
+#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1
-#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0xd1b4 0x7 0x2
+#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2
#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0
#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0
#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1
#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1
#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1
-#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0xd1c0 0x7 0x2
+#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2
#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0
#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0
#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0
#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1
#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1
#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1
-#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0xd1c4 0x7 0x2
+#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2
#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0
#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0
#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0
#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3
#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3
#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2
+#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0
projects / linux.git / commitdiff