MLK-16527 mmc: cqhci: fix function cqhci_set_irqs()

When we want to use some certain cqhci irq, we use the following
function to enable certain irq by pass the value to parameter 'set',

  void cqhci_set_irqs(struct cqhci_host *cq_host, u32 set)

Currently, driver use '|=' to set the ISGE and ISTE. But when we
want to clear all cqhci irq, by send 0 to the parameter 'set',
'|=' operation do not work.

This patch change to directly write the parameter 'set' to register
ISGE and ISTE, to fix this issue.

Without this patch, we may see the following dump massage when
cqhci driver do the recovery procress. For the bit 14 of the usdhc
interrupt status register, it is added for command queuing interrupt.
Currently our USDHC IC has a limitation, just confirm with IC team,
the bit 14 of register INT_STATUS_EN and INT_SIGNAL_EN can not mask
command queueing interrupt, this command queueing interrupt is impacted
by the CQIS. And CQIS can be masked by ISTE and ISGE.

[   35.225286] mmc0: running CQE recovery
[   35.229075] mmc0: Unexpected interrupt 0x00004000.
[   35.233870] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[   35.240315] mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00000002
[   35.246766] mmc0: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000008
[   35.253215] mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000033
[   35.259667] mmc0: sdhci: Present:   0x01fd8009 | Host ctl: 0x00000031
[   35.266117] mmc0: sdhci: Power:     0x00000002 | Blk gap:  0x00000080
[   35.272565] mmc0: sdhci: Wake-up:   0x00000008 | Clock:    0x0000000f
[   35.279013] mmc0: sdhci: Timeout:   0x0000008f | Int stat: 0x00004000
[   35.285466] mmc0: sdhci: Int enab:  0x007f1003 | Sig enab: 0x007f1003
[   35.291915] mmc0: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000502
[   35.298365] mmc0: sdhci: Caps:      0x07eb0000 | Caps_1:   0x8000b407
[   35.304815] mmc0: sdhci: Cmd:       0x00000cd3 | Max curr: 0x00ffffff
[   35.311266] mmc0: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0xffffffff
[   35.317716] mmc0: sdhci: Resp[2]:   0x328f5903 | Resp[3]:  0x00d02700
[   35.324163] mmc0: sdhci: Host ctl2: 0x00000008
[   35.328606] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x00000000
[   35.335054] mmc0: sdhci: ============================================

Fixes: 1aa50a573336 ("mmc: cqhci: support for command queue enabled host")
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index a3fc7ff..4b0dfa0 100644 (file)
--- a/drivers/mmc/host/cqhci.c
+++ b/drivers/mmc/host/cqhci.c
@@ -96,12 +96,8 @@ static void setup_trans_desc(struct cqhci_host *cq_host, u8 tag)
 
 static void cqhci_set_irqs(struct cqhci_host *cq_host, u32 set)
 {
-       u32 ier;
-
-       ier = cqhci_readl(cq_host, CQHCI_ISTE);
-       ier |= set;
-       cqhci_writel(cq_host, ier, CQHCI_ISTE);
-       cqhci_writel(cq_host, ier, CQHCI_ISGE);
+       cqhci_writel(cq_host, set, CQHCI_ISTE);
+       cqhci_writel(cq_host, set, CQHCI_ISGE);
 }
 
 #define DRV_NAME "cqhci"