int id;
struct flexcan_stop_mode stm;
+ /* Selects the clock source to CAN Protocol Engine (PE), 1 by default*/
+ u32 clk_src;
+
u32 mb_size;
u32 mb_num;
};
FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
};
+static struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
+ FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
+};
+
static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
if (err)
return err;
- reg = priv->read(®s->ctrl);
- reg |= FLEXCAN_CTRL_CLK_SRC;
- priv->write(reg, ®s->ctrl);
+ if (priv->clk_src) {
+ reg = priv->read(®s->ctrl);
+ reg |= FLEXCAN_CTRL_CLK_SRC;
+ priv->write(reg, ®s->ctrl);
+ }
err = flexcan_chip_enable(priv);
if (err)
}
static const struct of_device_id flexcan_of_match[] = {
+ { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
struct flexcan_regs __iomem *regs;
int err, irq;
u32 clock_freq = 0;
+ u32 clk_src = 1;
int wakeup = 1;
reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
else if (IS_ERR(reg_xceiver))
reg_xceiver = NULL;
- if (pdev->dev.of_node)
+ if (pdev->dev.of_node) {
of_property_read_u32(pdev->dev.of_node,
"clock-frequency", &clock_freq);
+ of_property_read_u32(pdev->dev.of_node,
+ "clk-src", &clk_src);
+ }
if (!clock_freq) {
clk_ipg = devm_clk_get(&pdev->dev, "ipg");
}
priv->dev = &pdev->dev;
+ priv->clk_src = clk_src;
priv->can.clock.freq = clock_freq;
priv->can.bittiming_const = &flexcan_bittiming_const;
priv->can.data_bittiming_const = &flexcan_fd_data_bittiming_const;