MLK-11376-01 ARM: dts: add dts file for imx6qp

Add dtsi and dts file for i.MX6QP

Signed-off-by: Bai Ping <b51503@freescale.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5f37837..6d72a1b 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -389,6 +389,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6q-phytec-pbab01.dtb \
        imx6q-rex-pro.dtb \
        imx6q-sabreauto.dtb \
+       imx6qp-sabreauto.dtb \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb \
        imx6q-sbc6x.dtb \

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index f18bab9..096e5ae 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -13,7 +13,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-       memory {
+       memory: memory {
                reg = <0x10000000 0x80000000>;
        };
 

diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts
index 5ce3840..e521ea3 100644 (file)
--- a/arch/arm/boot/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts
@@ -50,6 +50,10 @@
        compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
 };
 
+&fec {
+       pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+};
+
 &i2c2 {
        max7322: gpio@68 {
                compatible = "maxim,max7322";
@@ -85,7 +89,38 @@
 };
 
 &pcie {
-       status = "disabled";
+       reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&pre1 {
+       status = "okay";
+};
+
+&pre2 {
+       status = "okay";
+};
+
+&pre3 {
+       status = "okay";
+};
+
+&pre4 {
+       status = "okay";
+};
+
+&prg1 {
+       memory-region = <&memory>;
+       status = "okay";
+};
+
+&prg2 {
+       memory-region = <&memory>;
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
 };
 
 &vgen3_reg {

diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index 886dbf2..3762982 100644 (file)
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -43,6 +43,15 @@
 #include "imx6q.dtsi"
 
 / {
+       aliases {
+               pre0 = &pre1;
+               pre1 = &pre2;
+               pre2 = &pre3;
+               pre3 = &pre4;
+               prg0 = &prg1;
+               prg1 = &prg2;
+       };
+
        soc {
                ocram2: sram@00940000 {
                        compatible = "mmio-sram";
@@ -56,6 +65,89 @@
                        clocks = <&clks IMX6QDL_CLK_OCRAM>;
                };
 
+               pcie: pcie@0x01000000 {
+                       compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+                       reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
+                                 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
+                                <&clks IMX6QDL_CLK_SATA_REF_100M>,
+                                <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
+                       clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
+                       status = "disabled";
+               };
+
+               aips-bus@02100000 { /* AIPS2 */
+                       pre1: pre@021c8000 {
+                               compatible = "fsl,imx6q-pre";
+                               reg = <0x021c8000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRE0>;
+                               interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
+                               ocram = <&ocram2>;
+                               status = "disabled";
+                       };
+
+                       pre2: pre@021c9000 {
+                               compatible = "fsl,imx6q-pre";
+                               reg = <0x021c9000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRE1>;
+                               interrupts = <0 97 IRQ_TYPE_EDGE_RISING>;
+                               ocram = <&ocram2>;
+                               status = "disabled";
+                       };
+
+                       pre3: pre@021ca000 {
+                               compatible = "fsl,imx6q-pre";
+                               reg = <0x021ca000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRE2>;
+                               interrupts = <0 98 IRQ_TYPE_EDGE_RISING>;
+                               ocram = <&ocram3>;
+                               status = "disabled";
+                       };
+
+                       pre4: pre@021cb000 {
+                               compatible = "fsl,imx6q-pre";
+                               reg = <0x021cb000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRE3>;
+                               interrupts = <0 99 IRQ_TYPE_EDGE_RISING>;
+                               ocram = <&ocram3>;
+                               status = "disabled";
+                       };
+
+                       prg1: prg@021cc000 {
+                               compatible = "fsl,imx6q-prg";
+                               reg = <0x021cc000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRG0_AXI>,
+                                        <&clks IMX6QDL_CLK_PRG0_APB>;
+                               clock-names = "axi", "apb";
+                               gpr = <&gpr>;
+                               status = "disabled";
+                       };
+
+                       prg2: prg@021cd000 {
+                               compatible = "fsl,imx6q-prg";
+                               reg = <0x021cd000 0x1000>;
+                               clocks = <&clks IMX6QDL_CLK_PRG1_AXI>,
+                                        <&clks IMX6QDL_CLK_PRG1_APB>;
+                               clock-names = "axi", "apb";
+                               gpr = <&gpr>;
+                               status = "disabled";
+                       };
+               };
+
                ipu1: ipu@02400000 {
                        compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
                        clocks = <&clks IMX6QDL_CLK_IPU1>,
@@ -87,3 +179,8 @@
                };
        };
 };
+
+&ldb {
+       compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb";
+};
+