ARM: dts: imx6qdl-sabreauto: use internal version of adv7180 driver

change compatible string to use internal version of adv7180 driver

Signed-off-by: Robby Cai <robby.cai@nxp.com>

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index cd80631..9781df4 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -91,6 +91,14 @@
                regulator-always-on;
        };
 
+       reg_3p3v: 3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "3P3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
        reg_usb_h1_vbus: regulator-usb-h1-vbus {
                compatible = "regulator-fixed";
                regulator-name = "usb_h1_vbus";
@@ -281,19 +289,22 @@
                        #size-cells = <0>;
                        reg = <1>;
 
-                       adv7180: camera@21 {
-                               compatible = "adi,adv7180";
+                       adv7180: adv7180@21 {
+                               compatible = "adv,adv7180";
                                reg = <0x21>;
-                               powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
-                               interrupt-parent = <&gpio1>;
-                               interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
-                               port {
-                                       adv7180_to_ipu1_csi0_mux: endpoint {
-                                               remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
-                                               bus-width = <8>;
-                                       };
-                               };
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ipu1_1>;
+                               clocks = <&clks IMX6QDL_CLK_CKO>;
+                               clock-names = "csi_mclk";
+                               DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
+                               AVDD-supply = <&reg_3p3v>;  /* 1.8v */
+                               DVDD-supply = <&reg_3p3v>;  /* 1.8v */
+                               PVDD-supply = <&reg_3p3v>;  /* 1.8v */
+                               pwn-gpios = <&max7310_b 2 0>;
+                               csi_id = <0>;
+                               mclk = <24000000>;
+                               mclk_source = <0>;
+                               cvbs = <1>;
                        };
 
                        max7310_a: gpio@30 {
@@ -363,7 +374,10 @@
 };
 
 &ipu1_csi0_mux_from_parallel_sensor {
+       /* Downstream driver doesn't use endpoints */
+       /*
        remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+        */
        bus-width = <8>;
 };
 
@@ -775,6 +789,30 @@
                        >;
                };
 
+               pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
+                       fsl,pins = <
+                               MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
+                               MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
+                               MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
+                               MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
+                               MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
+                               MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
+                               MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
+                               MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
+                               MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
+                               MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
+                               MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
+                               MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
+                               MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
+                               MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
+                               MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
+                               MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
+                               MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+                               MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
+                               MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
+                       >;
+               };
+
                pinctrl_i2c3: i2c3grp {
                        fsl,pins = <
                                MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1