MLK-20125 ata: imx: add one ext_osc parameter for imx8qm ahci

Add one parameter to distinguish the different ref_clk
source, internal pll or the external osc.
NOTE: The value of the ext_osc should be aligned to the one
of the pcie's, since both of them share one ref_clk source.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 1cc7ffc..08eb112 100644 (file)
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -150,6 +150,7 @@ struct imx_ahci_priv {
        bool first_time;
        u32 phy_params;
        u32 imped_ratio;
+       u32 ext_osc;
 };
 
 void *sg_io_buffer_hack;
@@ -574,18 +575,32 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
                        IMX8QM_PHY_MODE_MASK,
                        IMX8QM_PHY_MODE_SATA);
 
-       /*
-        * BIT0 RXENA 1, BIT1 TXENA 0
-        * BIT12 PHY_X1_EPCS_SEL 1.
-        */
-       regmap_update_bits(imxpriv->gpr,
-                       IMX8QM_CSR_MISC_OFFSET,
-                       IMX8QM_MISC_IOB_RXENA,
-                       IMX8QM_MISC_IOB_RXENA);
-       regmap_update_bits(imxpriv->gpr,
-                       IMX8QM_CSR_MISC_OFFSET,
-                       IMX8QM_MISC_IOB_TXENA,
-                       0);
+       if (imxpriv->ext_osc) {
+               dev_info(dev, "external osc is used.\n");
+               /*
+                * bit0 rx ena 1, bit1 tx ena 0
+                * bit12 PHY_X1_EPCS_SEL 1.
+                */
+               regmap_update_bits(imxpriv->gpr,
+                               IMX8QM_CSR_MISC_OFFSET,
+                               IMX8QM_MISC_IOB_RXENA,
+                               IMX8QM_MISC_IOB_RXENA);
+               regmap_update_bits(imxpriv->gpr,
+                               IMX8QM_CSR_MISC_OFFSET,
+                               IMX8QM_MISC_IOB_TXENA,
+                               0);
+       } else {
+               dev_info(dev, "internal pll is used.\n");
+               regmap_update_bits(imxpriv->gpr,
+                               IMX8QM_CSR_MISC_OFFSET,
+                               IMX8QM_MISC_IOB_RXENA,
+                               0);
+               regmap_update_bits(imxpriv->gpr,
+                               IMX8QM_CSR_MISC_OFFSET,
+                               IMX8QM_MISC_IOB_TXENA,
+                               IMX8QM_MISC_IOB_TXENA);
+
+       }
        regmap_update_bits(imxpriv->gpr,
                        IMX8QM_CSR_MISC_OFFSET,
                        IMX8QM_MISC_PHYX1_EPCS_SEL,
@@ -1100,8 +1115,21 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
        struct platform_device *pdev = imxpriv->ahci_pdev;
        struct device_node *np = dev->of_node;
 
-       if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
+       if (of_property_read_u32(np, "ext_osc", &imxpriv->ext_osc) < 0) {
+               dev_info(dev, "ext_osc is not specified.\n");
+               /* Use the external osc as ref clk defaultly. */
+               imxpriv->ext_osc = 1;
+       }
+
+       if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) {
+               /*
+                * Regarding to the differnet Hw designs,
+                * Set the impedance ratio to 0x6c when 85OHM is used.
+                * Keep it to default value 0x80, when 100OHM is used.
+                */
+               dev_info(dev, "phy impedance ratio is not specified.\n");
                imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
+       }
        phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
        if (phy_res) {
                imxpriv->phy_base = devm_ioremap(dev, phy_res->start,