MLK-22293-6 clk-imx8: Add SATA relevant clock for iMX8QM

Add the SATA clocks to clk-imx8, so we can use clk uclass interfaces
to access the clocks in AHCI driver.

Signed-off-by: Ye Li <ye.li@nxp.com>

diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index 5ff7f5c..c6f5e30 100644 (file)
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -255,6 +255,7 @@ static struct imx8_fixed_clks imx8qm_fixed_clks[] = {
        { IMX8QM_MIPI0_CLK_ROOT, "MIPI0_CLK", SC_120MHZ },
        { IMX8QM_MIPI1_CLK_ROOT, "MIPI1_CLK", SC_120MHZ },
        { IMX8QM_HDMI_RX_IPG_CLK, "HDMI_RX_IPG_CLK", SC_200MHZ },
+       { IMX8QM_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ },
 };
 
 static struct imx8_gpr_clks imx8qm_gpr_clks[] = {
@@ -368,6 +369,20 @@ static struct imx8_lpcg_clks imx8qm_lpcg_clks[] = {
        { IMX8QM_GPMI_BCH_IO_CLK, "GPMI_IO_CLK", 4, NAND_LPCG, IMX8QM_GPMI_BCH_IO_DIV },
        { IMX8QM_GPMI_BCH_CLK, "GPMI_BCH_CLK", 0, NAND_LPCG, IMX8QM_GPMI_BCH_DIV },
        { IMX8QM_APBHDMA_CLK, "GPMI_CLK", 16, NAND_LPCG + 0x4, IMX8QM_AXI_CONN_CLK_ROOT },
+
+       { IMX8QM_HSIO_PHY_X1_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_CRR1_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X2_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X2_CRR0_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_MISC_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_MISC_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X2_APB_0_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X2_APB_1_CLK, "HSIO_PHY_X1_PER_CLK", 20, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_SATA_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_SATA_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_GPIO_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_GPIO_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PER_CLK", 0, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X2_PCLK_0, "HSIO_PHY_X1_PER_CLK", 0, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_PHY_X2_PCLK_1, "HSIO_PHY_X1_PER_CLK", 4, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_SATA_EPCS_RX_CLK, "HSIO_PHY_X1_PER_CLK", 8, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK },
+       { IMX8QM_HSIO_SATA_EPCS_TX_CLK, "HSIO_PHY_X1_PER_CLK", 4, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK },
 };
 
 struct imx8_mux_clks imx8qm_mux_clks[] = {