MLK-12757-1 ARM: dts: imx6ull-ddr3-arm2.dts: change usdhc2 pad setting

According to Hardware team's suggestion, for usdhc2, this patch change
the drive strength for clock pin and data pin, which can make the signal
meet the requirement for DDR50 mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>

diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
index 2c35f41..96cf48a 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
@@ -839,11 +839,11 @@
                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
                        fsl,pins = <
                                MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
-                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
-                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170b9
-                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170b9
-                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170b9
-                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170b9
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170a9
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170a9
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170a9
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170a9
                        >;
                };