msleep(20);
}
-u8 pma_cmn_ready(state_struct *state)
+int pma_cmn_ready(state_struct *state)
{
u32 i;
return 0;
}
-u8 pma_rx_clk_signal_detect(state_struct *state)
+int pma_rx_clk_signal_detect(state_struct *state)
{
u32 i;
return 0;
}
-u32 pma_rx_clk_freq_detect(state_struct *state)
+int pma_rx_clk_freq_detect(state_struct *state)
{
u16 reg_val;
u32 rx_clk_freq;
return rx_clk_freq;
}
-u8 pma_pll_config(state_struct *state,
+int pma_pll_config(state_struct *state,
u32 rx_clk_freq,
clk_ratio_t clk_ratio,
tmds_bit_clock_ratio_t tmds_bit_clk_ratio,
void speedup_config(state_struct *state);
void arc_config(state_struct *state);
void pma_config(state_struct *state);
-u8 pma_cmn_ready(state_struct *state);
-u8 pma_rx_clk_signal_detect(state_struct *state);
-u32 pma_rx_clk_freq_detect(state_struct *state);
+int pma_cmn_ready(state_struct *state);
+int pma_rx_clk_signal_detect(state_struct *state);
+int pma_rx_clk_freq_detect(state_struct *state);
void pre_data_rate_change(state_struct *state);
-u8 pma_pll_config(state_struct *state, u32, clk_ratio_t, tmds_bit_clock_ratio_t, unsigned char);
+int pma_pll_config(state_struct *state, u32, clk_ratio_t, tmds_bit_clock_ratio_t, unsigned char);
clk_ratio_t clk_ratio_detect(state_struct *state, u32, u32, u8, pixel_encoding_t, tmds_bit_clock_ratio_t);
void phy_status(state_struct *state);
/* Check if the firmware is running */
ret = CDN_API_CheckAlive_blocking(state);
- if (ret < 0)
- return ret;
+ if (ret != 0) {
+ DRM_ERROR("NO HDMI RX FW running\n");
+ return -ENXIO;
+ }
/* Set driver and firmware active */
CDN_API_MainControl_blocking(state, 1, &sts);