MLK-11556-8 ARM: dts: imx6sl-evk: add epdc support

Add epdc support on i.MX6SoloLite EVK board.
Add 'compatible', 'clocks' property in common imx6sl.dtsi
enable pxp, pmic, epdc in imx6sl-evk.dts

Signed-off-by: Robby Cai <r63905@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index d1d84b2..6ca43f1 100644 (file)
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -161,6 +161,15 @@
        };
 };
 
+&epdc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_epdc_0>;
+        V3P3-supply = <&V3P3_reg>;
+        VCOM-supply = <&VCOM_reg>;
+        DISPLAY-supply = <&DISPLAY_reg>;
+        status = "okay";
+};
+
 &fec {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_fec>;
@@ -283,6 +292,73 @@
                compatible = "fsl,mma8450";
                reg = <0x1c>;
        };
+
+       max17135@48 {
+               compatible = "maxim,max17135";
+               reg = <0x48>;
+               vneg_pwrup = <1>;
+               gvee_pwrup = <2>;
+               vpos_pwrup = <10>;
+               gvdd_pwrup = <12>;
+               gvdd_pwrdn = <1>;
+               vpos_pwrdn = <2>;
+               gvee_pwrdn = <8>;
+               vneg_pwrdn = <10>;
+               gpio_pmic_pwrgood = <&gpio2 13 0>;
+               gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+               gpio_pmic_wakeup = <&gpio2 14 0>;
+               gpio_pmic_v3p3 = <&gpio2 7 0>;
+               gpio_pmic_intr = <&gpio2 12 0>;
+
+               regulators {
+                       DISPLAY_reg: DISPLAY {
+                               regulator-name = "DISPLAY";
+                       };
+
+                       GVDD_reg: GVDD {
+                               /* 20v */
+                               regulator-name = "GVDD";
+                       };
+
+                       GVEE_reg: GVEE {
+                               /* -22v */
+                               regulator-name = "GVEE";
+                       };
+
+                       HVINN_reg: HVINN {
+                               /* -22v */
+                               regulator-name = "HVINN";
+                       };
+
+                       HVINP_reg: HVINP {
+                               /* 20v */
+                               regulator-name = "HVINP";
+                       };
+
+                       VCOM_reg: VCOM {
+                               regulator-name = "VCOM";
+                               /* 2's-compliment, -4325000 */
+                               regulator-min-microvolt = <0xffbe0178>;
+                               /* 2's-compliment, -500000 */
+                               regulator-max-microvolt = <0xfff85ee0>;
+                       };
+
+                       VNEG_reg: VNEG {
+                               /* -15v */
+                               regulator-name = "VNEG";
+                       };
+
+                       VPOS_reg: VPOS {
+                               /* 15v */
+                               regulator-name = "VPOS";
+                       };
+
+                       V3P3_reg: V3P3 {
+                               regulator-name = "V3P3";
+                       };
+               };
+       };
+
 };
 
 &i2c2 {
@@ -389,6 +465,39 @@
                        >;
                };
 
+                pinctrl_epdc_0: epdcgrp-0 {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_D0__EPDC_DATA00  0x80000000
+                                MX6SL_PAD_EPDC_D1__EPDC_DATA01  0x80000000
+                                MX6SL_PAD_EPDC_D2__EPDC_DATA02  0x80000000
+                                MX6SL_PAD_EPDC_D3__EPDC_DATA03  0x80000000
+                                MX6SL_PAD_EPDC_D4__EPDC_DATA04  0x80000000
+                                MX6SL_PAD_EPDC_D5__EPDC_DATA05  0x80000000
+                                MX6SL_PAD_EPDC_D6__EPDC_DATA06  0x80000000
+                                MX6SL_PAD_EPDC_D7__EPDC_DATA07  0x80000000
+                                MX6SL_PAD_EPDC_D8__EPDC_DATA08  0x80000000
+                                MX6SL_PAD_EPDC_D9__EPDC_DATA09  0x80000000
+                                MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
+                                MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
+                                MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
+                                MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
+                                MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
+                                MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
+                                MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
+                                MX6SL_PAD_EPDC_GDSP__EPDC_GDSP   0x80000000
+                                MX6SL_PAD_EPDC_GDOE__EPDC_GDOE   0x80000000
+                                MX6SL_PAD_EPDC_GDRL__EPDC_GDRL   0x80000000
+                                MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
+                                MX6SL_PAD_EPDC_SDOE__EPDC_SDOE   0x80000000
+                                MX6SL_PAD_EPDC_SDLE__EPDC_SDLE   0x80000000
+                                MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
+                                MX6SL_PAD_EPDC_BDR0__EPDC_BDR0   0x80000000
+                                MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
+                                MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
+                                MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
+                        >;
+                };
+
                pinctrl_fec: fecgrp {
                        fsl,pins = <
                                MX6SL_PAD_FEC_MDC__FEC_MDC              0x1b0b0
@@ -665,6 +774,10 @@
        };
 };
 
+&pxp {
+       status = "okay";
+};
+
 &kpp {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_kpp>;

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index d906634..f626f2c 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -771,13 +771,20 @@
                        };
 
                        pxp: pxp@020f0000 {
+                               compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
                                reg = <0x020f0000 0x4000>;
                                interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
+                               clock-names = "pxp-axi", "disp-axi";
+                               status = "disabled";
                        };
 
                        epdc: epdc@020f4000 {
+                               compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
                                reg = <0x020f4000 0x4000>;
                                interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
+                               clock-names = "epdc_axi", "epdc_pix";
                        };
 
                        lcdif: lcdif@020f8000 {