MLK-24012-05 arm64: dts: add imx8qm pciea ep support

Add the iMX8QM PCIEA EP support and verified on MEK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 93a2340..1c586d8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
                          imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \
                          imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \
                          imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \
+                         imx8qm-mek-pcie-ep.dtb \
                          imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \
                          imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \
                          imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts
new file mode 100644 (file)
index 0000000..a1d9e6e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qm-mek.dts"
+
+&pciea{
+       status = "disabled";
+};
+
+&pcieb{
+       status = "disabled";
+};
+
+&pciea_ep{
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pciea>;
+       ext_osc = <1>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index e62957d..09fde14 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -135,6 +135,40 @@
                status = "disabled";
        };
 
+       pciea_ep: pcie_ep@0x5f000000 {
+               compatible = "fsl,imx8qm-pcie-ep";
+               reg = <0x5f000000 0x00010000>,
+                     <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */
+                     <0x60000000 0x10000000>;
+               reg-names = "regs", "hsio", "addr_space";
+               num-lanes = <1>;
+               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+               interrupt-names = "dma";
+               /*
+                * Set these clocks in default, then clocks should be
+                * refined for exact hw design of imx8 pcie.
+                */
+               clocks = <&pciea_lpcg 0>,
+                        <&pciea_lpcg 1>,
+                        <&pciea_lpcg 2>,
+                        <&phyx2_lpcg 0>,
+                        <&phyx2_crr0_lpcg 0>,
+                        <&pciea_crr2_lpcg 0>,
+                        <&misc_crr5_lpcg 0>;
+               clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+                             "pcie_phy", "phy_per", "pcie_per", "misc_per";
+               power-domains = <&pd IMX_SC_R_PCIE_A>,
+                               <&pd IMX_SC_R_SERDES_0>,
+                               <&pd IMX_SC_R_HSIO_GPIO>;
+               power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+               fsl,max-link-speed = <3>;
+               hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+               local-addr = <0x40000000>;
+               num-ib-windows = <6>;
+               num-ob-windows = <6>;
+               status = "disabled";
+       };
+
        pcieb: pcie@0x5f010000 {
                compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
                reg = <0x5f010000 0x10000>, /* Controller reg */