MLK-13022-1 arm: dts: new dts for eMMC support on i.MX6ULL EVK reworked board

Enable eMMC for i.MX6ULL EVK rework board due to the pad conflict with NAND
and Micro-SD.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5e59697..09ba041 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -500,6 +500,7 @@ dtb-$(CONFIG_SOC_IMX6ULL) += \
        imx6ull-14x14-ddr3-arm2-wm8958.dtb \
        imx6ull-14x14-evk.dtb \
        imx6ull-14x14-evk-btwifi.dtb \
+       imx6ull-14x14-evk-emmc.dtb \
        imx6ull-14x14-evk-gpmi-weim.dtb \
        imx6ull-14x14-evk-usb-certi.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \

diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts
new file mode 100644 (file)
index 0000000..5097ec8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-14x14-evk.dts"
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+       pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+       assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>;
+       assigned-clock-rates = <0>, <176000000>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 24c9de4..e44fa9d 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -505,6 +505,51 @@
                        >;
                };
 
+               pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+                       >;
+               };
+
+               pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+                       >;
+               };
+
                pinctrl_wdog: wdoggrp {
                        fsl,pins = <
                                MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
@@ -689,10 +734,7 @@
 &usdhc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;
-       no-1-8-v;
        non-removable;
-       keep-power-in-suspend;
-       enable-sdio-wakeup;
        status = "okay";
 };