/*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
SC_P_ESAI0_TX3_RX2
SC_P_ESAI0_TX4_RX1
SC_P_ESAI0_TX5_RX0
+
+ /* lvds pwm */
+ SC_P_LVDS1_GPIO00
>;
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>,
&aud_rec_clk1_lpcg {
xen,passthrough;
};
+
+&lvds1_pwm {
+ xen,passthrough;
+};
clock-names = "apb_pclk";
};
+ lvds_backlight1: lvds_backlight@1 {
+ compatible = "pwm-backlight";
+ pwms = <&lvds1_pwm 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
passthrough {
compatible = "simple-bus";
ranges;
/delete-node/ &lvds_region1;
/delete-node/ &ldb1_phy;
/delete-node/ &ldb1;
-/delete-node/ &lvds1_pwm;
/*/delete-node/ &camera;*/
/delete-node/ &adc0;
/delete-node/ &adc1;
>;
};
+ pinctrl_lvds1_pwm0: lvds1pwm0grp {
+ fsl,pins = <
+ SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020
+ >;
+ };
+
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
SC_P_UART1_RX_DMA_UART1_RX 0x06000020
};
};
};
+
+&lvds1_pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1_pwm0>;
+ status = "okay";
+};