MLK-11429-1: ASoC: fsl_spdif: don't change the root clock rate of spdif in driver

cherry-pick below patch from imx_3.14.y
ENGR00331799-2 ASoC: fsl_spdif: don't change the root clock rate of spdif in driver

The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change the clock rate in driver.
In this patch remove the clk_set_rate and clk_round_rate to protect the
clock.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit c77170b2c9a9737f6fd61a5ea85a43b90e8ef02b)

diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 22964a2..36752df 100644 (file)
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1,7 +1,7 @@
 /*
  * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
  *
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
  *
  * Based on stmp3xxx_spdif_dai.c
  * Vladimir Barinov <vbarinov@embeddedalley.com>
@@ -381,7 +381,6 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
        unsigned long csfs = 0;
        u32 stc, mask, rate;
        u8 clk, txclk_df, sysclk_df;
-       int ret;
 
        switch (sample_rate) {
        case 32000:
@@ -423,19 +422,6 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
 
        sysclk_df = spdif_priv->sysclk_df[rate];
 
-       /* Don't mess up the clocks from other modules */
-       if (clk != STC_TXCLK_SPDIF_ROOT)
-               goto clk_set_bypass;
-
-       /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
-       ret = clk_set_rate(spdif_priv->txclk[rate],
-                          64 * sample_rate * txclk_df);
-       if (ret) {
-               dev_err(&pdev->dev, "failed to set tx clock rate\n");
-               return ret;
-       }
-
-clk_set_bypass:
        dev_dbg(&pdev->dev, "expected clock rate = %d\n",
                        (64 * sample_rate * txclk_df * sysclk_df));
        dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
@@ -1112,7 +1098,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
 {
        const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
        bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
-       u64 rate_ideal, rate_actual, sub;
+       u64 rate_actual, sub;
        u32 sysclk_dfmin, sysclk_dfmax;
        u32 txclk_df, sysclk_df, arate;
 
@@ -1122,11 +1108,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
 
        for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
                for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
-                       rate_ideal = rate[index] * txclk_df * 64;
-                       if (round)
-                               rate_actual = clk_round_rate(clk, rate_ideal);
-                       else
-                               rate_actual = clk_get_rate(clk);
+                       rate_actual = clk_get_rate(clk);
 
                        arate = rate_actual / 64;
                        arate /= txclk_df * sysclk_df;