This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.
Signed-off-by: Han Xu <b45815@freescale.com>
return status;
}
return status;
+ case CFI_MFR_ST: /* Micron, actually */
+ /* DTR quad read works with the Extended SPI protocol. */
+ return 0;
default:
return -EINVAL;
}
case SPI_NOR_DDR_QUAD:
if (JEDEC_MFR(info) == CFI_MFR_AMD) { /* Spansion */
nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
+ } else if (JEDEC_MFR(info) == CFI_MFR_ST) {
+ nor->read_opcode = SPINOR_OP_READ_1_1_4_D;
} else {
dev_err(dev, "DDR Quad Read is not supported.\n");
return -EINVAL;
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
-#define SPINOR_OP_READ_1_4_4_D 0xeb /* Read data bytes (DDR Quad SPI) */
+#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */
+#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */