MLK-13853-3 ARM64: dts: imx8qm: Enable SPDIF0

Add SPDIF0 node and the related EDMA configuration:
channels and interrupts. Comments provided for
component's related EDMA configuration given the
increased number of channels and interrupts.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index fe56767..9e41d5a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -1075,34 +1075,39 @@
 
        edma2: dma-controller@591F0000 {
                compatible = "fsl,imx8qm-adma";
-               reg = <0x0 0x59200000 0x0 0x10000>,
+               reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
                        <0x0 0x59210000 0x0 0x10000>,
                        <0x0 0x59220000 0x0 0x10000>,
                        <0x0 0x59230000 0x0 0x10000>,
                        <0x0 0x59240000 0x0 0x10000>,
                        <0x0 0x59250000 0x0 0x10000>,
-                       <0x0 0x59260000 0x0 0x10000>,
-                       <0x0 0x59270000 0x0 0x10000>,
-                       <0x0 0x592c0000 0x0 0x10000>,
-                       <0x0 0x592d0000 0x0 0x10000>;
+                       <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
+                       <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
+                       <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+                       <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+                       <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+                       <0x0 0x592d0000 0x0 0x10000>; /* sai0 tx */
                #dma-cells = <3>;
                shared-interrupt;
-               dma-channels = <10>;
-               interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+               dma-channels = <12>;
+               interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
                                <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
                                <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-                               <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-                               <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+                               <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
                                <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "edma-chan0-tx", "edma-chan1-tx",
+               interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */
                                "edma-chan2-tx", "edma-chan3-tx",
                                "edma-chan4-tx", "edma-chan5-tx",
-                               "edma-chan6-tx", "edma-chan7-tx",
-                               "edma-chan12-tx", "edma-chan13-tx";
+                               "edma-chan6-tx", "edma-chan7-tx", /* esai0 */
+                               "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */
+                               "edma-chan12-tx", "edma-chan13-tx"; /* sai0 */
                status = "okay";
        };
 
@@ -1388,6 +1393,32 @@
                status = "disabled";
        };
 
+       spdif0: spdif@59020000 {
+               compatible = "fsl,imx35-spdif";
+               reg = <0x0 0x59020000 0x0 0x10000>;
+               interrupts = /* <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, */ /* rx */
+                            <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+               clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */
+                       <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */
+                       <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */
+                       <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */
+                       <&clk IMX8QM_CLK_DUMMY>; /* spba */
+               clock-names = "core", "rxtx0",
+                             "rxtx1", "rxtx2",
+                             "rxtx3", "rxtx4",
+                             "rxtx5", "rxtx6",
+                             "rxtx7", "spba";
+               dmas = <&edma2 8 0 1>, <&edma2 9 0 0>;
+               dma-names = "rx", "tx";
+               power-domains = <&pd_spdif0>;
+               status = "disabled";
+       };
+
        sai0: sai@59040000 {
                compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
                reg = <0x0 0x59040000 0x0 0x10000>;