MLK-16986-1: phy: Fix Mixel PHY driver best_match

When setting up the CM, CN and CO decimal values for DPHY PLL, these
values should only be rounded up when a "best_match" is requested. Some
DSI receivers requires the DSI clock to be exactly matched with the
pixel clock.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com

diff --git a/drivers/phy/phy-mixel-mipi-dsi.c b/drivers/phy/phy-mixel-mipi-dsi.c
index cd7192d..0b00400 100644 (file)
--- a/drivers/phy/phy-mixel-mipi-dsi.c
+++ b/drivers/phy/phy-mixel-mipi-dsi.c
@@ -146,7 +146,8 @@ int mixel_phy_mipi_set_phy_speed(struct phy *phy,
        if (numerator < 16 || numerator > 255)
                return -EINVAL;
 
-       numerator = DIV_ROUND_UP(numerator, denominator) * denominator;
+       if (best_match)
+               numerator = DIV_ROUND_UP(numerator, denominator) * denominator;
 
        priv->divider.cn = 1;
        if (denominator > 8) {