MLK-17634-15: drm: imx: dcss: handle P010 format

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..3467cc0 100644 (file)
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -164,6 +164,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
                { .format = DRM_FORMAT_YVU444,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1, .is_yuv = true },
                { .format = DRM_FORMAT_NV12,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
                { .format = DRM_FORMAT_NV21,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+               { .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
                { .format = DRM_FORMAT_NV16,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
                { .format = DRM_FORMAT_NV61,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
                { .format = DRM_FORMAT_NV24,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c b/drivers/gpu/drm/imx/dcss/dcss-plane.c
index 338d375..0efbd97 100644 (file)
--- a/drivers/gpu/drm/imx/dcss/dcss-plane.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c
@@ -148,6 +148,7 @@ static bool dcss_plane_format_mod_supported(struct drm_plane *plane,
                switch (format) {
                case DRM_FORMAT_NV12:
                case DRM_FORMAT_NV21:
+               case DRM_FORMAT_P010:
                        return modifier == DRM_FORMAT_MOD_VSI_G1_TILED ||
                               modifier == DRM_FORMAT_MOD_VSI_G2_TILED ||
                               modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED;
@@ -299,7 +300,8 @@ static void dcss_plane_atomic_set_base(struct dcss_plane *dcss_plane)
        case DRM_PLANE_TYPE_OVERLAY:
                if (!modifiers_present ||
                    (pix_format != DRM_FORMAT_NV12 &&
-                    pix_format != DRM_FORMAT_NV21)) {
+                    pix_format != DRM_FORMAT_NV21 &&
+                    pix_format != DRM_FORMAT_P010)) {
                        dcss_dtrc_bypass(dcss_plane->dcss, dcss_plane->ch_num);
                        return;
                }
@@ -451,7 +453,7 @@ static void dcss_plane_atomic_update(struct drm_plane *plane,
 
        ipipe_cfg.pixel_format = pixel_format;
        ipipe_cfg.nl = NL_REC709;
-       ipipe_cfg.pr = PR_FULL;
+       ipipe_cfg.pr = PR_LIMITED;
        ipipe_cfg.g = G_REC709;
 
        dcss_crtc_get_opipe_cfg(state->crtc, &opipe_cfg);
@@ -459,6 +461,7 @@ static void dcss_plane_atomic_update(struct drm_plane *plane,
        /* apparently the other settins that are read from connector are not good,
         * so hardcode */
        opipe_cfg.nl = NL_REC709;
+       opipe_cfg.pr = PR_FULL;
        opipe_cfg.g = G_REC2020;
 
        dcss_hdr10_setup(dcss_plane->dcss, dcss_plane->ch_num,

diff --git a/drivers/gpu/imx/dcss/dcss-dpr.c b/drivers/gpu/imx/dcss/dcss-dpr.c
index aa11ba3..279f482 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-dpr.c
+++ b/drivers/gpu/imx/dcss/dcss-dpr.c
@@ -270,7 +270,9 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
        u32 gap = DCSS_DPR_FRAME_2P_BASE_ADDR - DCSS_DPR_FRAME_1P_BASE_ADDR;
        u32 pix_format = dpr->ch[ch_num].pix_format;
 
-       if (pix_format == DRM_FORMAT_NV12 || pix_format == DRM_FORMAT_NV21)
+       if (pix_format == DRM_FORMAT_NV12 ||
+           pix_format == DRM_FORMAT_NV21 ||
+           pix_format == DRM_FORMAT_P010)
                max_planes = 2;
 
        for (plane = 0; plane < max_planes; plane++) {
@@ -477,6 +479,7 @@ static void dcss_dpr_rtram_set(struct dcss_soc *dcss, int ch_num,
        switch (pix_format) {
        case DRM_FORMAT_NV21:
        case DRM_FORMAT_NV12:
+       case DRM_FORMAT_P010:
                ch->rtram_3buf_en = 1;
                ch->rtram_4line_en = 0;
                break;
@@ -556,6 +559,7 @@ static int dcss_dpr_get_bpp(u32 pix_format)
        switch (pix_format) {
        case DRM_FORMAT_NV12:
        case DRM_FORMAT_NV21:
+       case DRM_FORMAT_P010:
                bpp = 8;
                break;
 

diff --git a/drivers/gpu/imx/dcss/dcss-dtg.c b/drivers/gpu/imx/dcss/dcss-dtg.c
index bbb52f3..441903e 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-dtg.c
+++ b/drivers/gpu/imx/dcss/dcss-dtg.c
@@ -195,7 +195,7 @@ int dcss_dtg_init(struct dcss_soc *dcss, unsigned long dtg_base)
        dtg->alpha = 255;
        dtg->use_global = 0;
 
-       dtg->control_status |= BLENDER_VIDEO_ALPHA_SEL |
+       dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |
                ((dtg->alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK);
 
        return 0;
@@ -299,7 +299,8 @@ static bool dcss_dtg_global_alpha_needed(u32 pix_format)
               pix_format == DRM_FORMAT_YUYV        ||
               pix_format == DRM_FORMAT_YVYU        ||
               pix_format == DRM_FORMAT_NV12        ||
-              pix_format == DRM_FORMAT_NV21;
+              pix_format == DRM_FORMAT_NV21        ||
+              pix_format == DRM_FORMAT_P010;
 }
 
 bool dcss_dtg_global_alpha_changed(struct dcss_soc *dcss, int ch_num,

diff --git a/drivers/gpu/imx/dcss/dcss-scaler.c b/drivers/gpu/imx/dcss/dcss-scaler.c
index 7ad5ccc..1a28999 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-scaler.c
+++ b/drivers/gpu/imx/dcss/dcss-scaler.c
@@ -290,7 +290,8 @@ static void dcss_scaler_res_set(struct dcss_soc *dcss, int ch_num,
            pix_format == DRM_FORMAT_YUYV || pix_format == DRM_FORMAT_YVYU)
                csrc_xres >>= 1;
        else if (pix_format == DRM_FORMAT_NV12 ||
-                pix_format == DRM_FORMAT_NV21) {
+                pix_format == DRM_FORMAT_NV21 ||
+                pix_format == DRM_FORMAT_P010) {
                csrc_xres >>= 1;
                csrc_yres >>= 1;
        }
@@ -349,7 +350,8 @@ static bool dcss_scaler_fractions_set(struct dcss_soc *dcss, int ch_num,
            pix_format == DRM_FORMAT_YUYV || pix_format == DRM_FORMAT_YVYU) {
                c_hinc >>= 1;
        } else if (pix_format == DRM_FORMAT_NV12 ||
-                  pix_format == DRM_FORMAT_NV21) {
+                  pix_format == DRM_FORMAT_NV21 ||
+                  pix_format == DRM_FORMAT_P010) {
                c_hinc >>= 1;
                c_vinc >>= 1;
        }
@@ -602,7 +604,8 @@ void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format,
                dcss_scaler_yuv_enable(dcss, ch_num, true);
 
                if (pix_format == DRM_FORMAT_NV12 ||
-                   pix_format == DRM_FORMAT_NV21) {
+                   pix_format == DRM_FORMAT_NV21 ||
+                   pix_format == DRM_FORMAT_P010) {
                        rtr_8line_en = true;
                        src_format = BUF_FMT_YUV420;
                } else if (pix_format == DRM_FORMAT_UYVY ||