MLK-19252-3 drm/bridge: sec-dsim: workaround 3 data lanes case

According to a lot of tests and debug, for the Non-Burst with
Sync Pulse mode with 3 data lanes enable, the DSI peripheral
ADV7535 cannot display correctly, but the output timings seems
to be correct. Until now, the root cause for this issue still
cannot be found. So make this workaround to force to use 2 data
lanes when meeting the 3 lanes requests.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 6e7bc3bfd5b03da698a4024199bb696b792cc14e)
(cherry picked from commit 14f43f0aef26418e10f7840db726e990e557a2d1)
(cherry picked from commit 28dfae13bc259a99b8ee15f95e65b48cc7dbb2f8)

diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
index 70e4e1a..e2b0e8a 100644 (file)
--- a/drivers/gpu/drm/bridge/sec-dsim.c
+++ b/drivers/gpu/drm/bridge/sec-dsim.c
@@ -367,6 +367,13 @@ static int sec_mipi_dsim_host_attach(struct mipi_dsi_host *host,
                dsim->panel = panel;
        }
 
+       /* TODO: DSIM 3 lanes has some display issue, so
+        * avoid 3 lanes enable, and force data lanes to
+        * be 2.
+        */
+       if (dsi->lanes == 3)
+               dsi->lanes = 2;
+
        dsim->lanes      = dsi->lanes;
        dsim->channel    = dsi->channel;
        dsim->format     = dsi->format;