MLK-13707 ARM: dts: move cd/vsel/rst/wp pin out of pinctrl_hog_1

For 7ULP, when system suspend, it will in VLLS mode, all pad config
will lost when system resume. For vsel pin, if lost, I/O voltage can't
change from 3.3v to 1.8v, for cd/wp pin, card detect and write protect
function will also not work. So for usdhc cd/wp/rst/vsel pad, need
to set again after system resume, so move this pin out of pinctrl_hog_1.

Besides, cd/wp pin need to be config as GPIO input mode, and rst pin
need to be config to GPIO output mode. This patch also clear the OBE
for cd/wp pin, and clear the IBE for rst pin, otherwise system can't
detect SD3.0 card due to the wrong pad setting.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 314597864b1d8cad54bae7d4c6289830156eb088)

diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 13d00f2..1009eff 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -166,12 +166,7 @@
        imx7ulp-evk {
                pinctrl_hog_1: hoggrp-1 {
                        fsl,pins = <
-                               ULP1_PAD_PTC10__PTC10           0x30100         /* USDHC0 CD */
                                ULP1_PAD_PTC1__PTC1             0x20100
-                               ULP1_PAD_PTD0__PTD0             0x30100         /* USDHC0 RST */
-                               ULP1_PAD_PTE13__PTE13           0x30103         /* USDHC1 CD */
-                               ULP1_PAD_PTE12__PTE12           0x30103         /* USDHC1 WP */
-                               ULP1_PAD_PTE14__SDHC1_VS        0x843           /* USDHC1 VSEL */
                        >;
                };
 
@@ -228,6 +223,8 @@
                                ULP1_PAD_PTD8__SDHC0_D2         0x843
                                ULP1_PAD_PTD9__SDHC0_D1         0x843
                                ULP1_PAD_PTD10__SDHC0_D0        0x843
+                               ULP1_PAD_PTC10__PTC10           0x10100         /* USDHC0 CD */
+                               ULP1_PAD_PTD0__PTD0             0x20100         /* USDHC0 RST */
                        >;
                };
 
@@ -287,7 +284,10 @@
 
                pinctrl_usdhc1_rst: usdhc1grp_rst {
                        fsl,pins = <
-                               ULP1_PAD_PTE11__PTE11                   0x30100 /* USDHC1 RST */
+                               ULP1_PAD_PTE11__PTE11           0x20100         /* USDHC1 RST */
+                               ULP1_PAD_PTE13__PTE13           0x10103         /* USDHC1 CD */
+                               ULP1_PAD_PTE12__PTE12           0x10103         /* USDHC1 WP */
+                               ULP1_PAD_PTE14__SDHC1_VS        0x843           /* USDHC1 VSEL */
                        >;
                };