MLK-16698-2: arm64: dts: fsl-imx8qm-lpddr4-arm2: Enable mipi-dsi with rm67191

Enable the MIPI-DSI to RM67191 OLED display panel path on the MX8QM
LPDDR4 development board.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index dc8bd01..cbefb88 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -16,7 +16,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
                                 fsl-imx8qm-lpddr4-arm2-spdif.dtb \
                                 fsl-imx8qm-lpddr4-arm2-mqs.dtb \
                                 fsl-imx8qm-lpddr4-arm2-usb3.dtb \
-                                fsl-imx8qm-lpddr4-arm2-dsi-adv7535.dtb
+                                fsl-imx8qm-lpddr4-arm2-dsi-adv7535.dtb \
+                                fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dtb
 dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
                                  fsl-imx8qxp-mek.dtb \
                                  fsl-imx8qxp-mek-enet2.dtb \

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts
new file mode 100644 (file)
index 0000000..fee1253
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qm-lpddr4-arm2.dts"
+
+&hdmi {
+       status = "disabled";
+};
+
+&ldb1_phy {
+       status = "disabled";
+};
+
+&ldb1 {
+       status = "disabled";
+};
+
+&ldb2_phy {
+       status = "disabled";
+};
+
+&ldb2 {
+       status = "disabled";
+};
+
+&mipi_dsi_phy1 {
+       status = "okay";
+};
+
+&mipi_dsi1 {
+       status = "okay";
+
+       panel@0 {
+               compatible = "raydium,rm67191";
+               reg = <0>;
+               pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>;
+               reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+               dsi-lanes = <4>;
+               panel-width-mm = <68>;
+               panel-height-mm = <121>;
+               port {
+                       panel1_in: endpoint {
+                               remote-endpoint = <&mipi1_out>;
+                       };
+               };
+       };
+
+       port@1 {
+               mipi1_out: endpoint {
+                       remote-endpoint = <&panel1_in>;
+               };
+       };
+};
+
+&mipi_dsi_phy2 {
+       status = "okay";
+};
+
+&mipi_dsi2 {
+       status = "okay";
+
+       panel@0 {
+               compatible = "raydium,rm67191";
+               reg = <0>;
+               pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>;
+               reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+               dsi-lanes = <4>;
+               panel-width-mm = <68>;
+               panel-height-mm = <121>;
+               port {
+                       panel2_in: endpoint {
+                               remote-endpoint = <&mipi2_out>;
+                       };
+               };
+       };
+
+       port@1 {
+               mipi2_out: endpoint {
+                       remote-endpoint = <&panel2_in>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 6d89c96..44f09a7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -297,6 +297,12 @@
                        >;
                };
 
+               pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
+                       fsl,pins = <
+                               SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07             0x00000021
+                       >;
+               };
+
                pinctrl_lpi2c0: lpi2c0grp {
                        fsl,pins = <
                                SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL   0xc600004c