MLK-10500: arm: imx: clk-pllv3: fix AV pll num denom offsets

* Fix PLL Audio/Video Numerator/Denominator register offsets
* In imx7d pll register CCM_ANALOG_PLL_VIDEO_NUM and
  CCM_ANALOG_PLL_VIDEO_DENOM offset is different with imx6.
  For imx7D the correct setting should be:
  PLL_NUM_OFFSET         0x20
  PLL_DENOM_OFFSET       0x30
* Add additional macros to handle imx7d audio/video
  pll num/demom offset settings.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
[Octavian: use IMX_PLLV3_AV_IMX7 instead of cpu_is_imx7d()]
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index ff1c0b2..61436ab 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -424,11 +424,11 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
 
        clks[IMX7D_PLL_ARM_MAIN]  = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f);
-       clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_dram_main", "osc", base + 0x70, 0x7f);
+       clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);
        clks[IMX7D_PLL_SYS_MAIN]  = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
        clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
-       clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);
-       clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);
+       clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);
+       clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);
 
        clks[IMX7D_PLL_ARM_MAIN_BYPASS]  = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
        clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 7a6acc3..f62d285 100644 (file)
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -18,8 +18,10 @@
 #include <linux/err.h>
 #include "clk.h"
 
-#define PLL_NUM_OFFSET         0x10
-#define PLL_DENOM_OFFSET       0x20
+#define PLL_NUM_OFFSET                 0x10
+#define PLL_DENOM_OFFSET               0x20
+#define PLL_AV_IMX7_NUM_OFFSET         0x20
+#define PLL_AV_IMX7_DENOM_OFFSET       0x30
 
 #define BM_PLL_POWER           (0x1 << 12)
 #define BM_PLL_LOCK            (0x1 << 31)
@@ -45,6 +47,8 @@ struct clk_pllv3 {
        u32             div_mask;
        u32             div_shift;
        unsigned long   ref_clock;
+       u32             num_offset;
+       u32             denom_offset;
 };
 
 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -215,8 +219,8 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
                                              unsigned long parent_rate)
 {
        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-       u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
-       u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
+       u32 mfn = readl_relaxed(pll->base + pll->num_offset);
+       u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
        u32 div = readl_relaxed(pll->base) & pll->div_mask;
        u64 temp64 = (u64)parent_rate;
 
@@ -277,8 +281,8 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
        val &= ~pll->div_mask;
        val |= div;
        writel_relaxed(val, pll->base);
-       writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
-       writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
+       writel_relaxed(mfn, pll->base + pll->num_offset);
+       writel_relaxed(mfd, pll->base + pll->denom_offset);
 
        return clk_pllv3_wait_lock(pll);
 }
@@ -321,6 +325,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                return ERR_PTR(-ENOMEM);
 
        pll->power_bit = BM_PLL_POWER;
+       pll->num_offset = PLL_NUM_OFFSET;
+       pll->denom_offset = PLL_DENOM_OFFSET;
 
        switch (type) {
        case IMX_PLLV3_SYS:
@@ -332,6 +338,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                ops = &clk_pllv3_ops;
                pll->powerup_set = true;
                break;
+       case IMX_PLLV3_AV_IMX7:
+               pll->num_offset = PLL_AV_IMX7_NUM_OFFSET;
+               pll->denom_offset = PLL_AV_IMX7_DENOM_OFFSET;
+               /* fall through */
        case IMX_PLLV3_AV:
                ops = &clk_pllv3_av_ops;
                break;

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 3799ff8..f3664c7 100644 (file)
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -34,6 +34,7 @@ enum imx_pllv3_type {
        IMX_PLLV3_AV,
        IMX_PLLV3_ENET,
        IMX_PLLV3_ENET_IMX7,
+       IMX_PLLV3_AV_IMX7,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,