KVM: arm64: Flush the instruction cache if not unmapping the VM on reboot

On a system with FWB, we don't need to unmap Stage-2 on reboot,
as even if userspace takes this opportunity to repaint the whole
of memory, FWB ensures that the data side stays consistent even
if the guest uses non-cacheable mappings.

However, the I-side is not necessarily coherent with the D-side
if CTR_EL0.DIC is 0. In this case, invalidate the i-cache to
preserve coherency.

Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Fixes: 892713e97ca1 ("KVM: arm64: Sidestep stage2_unmap_vm() on vcpu reset when S2FWB is supported")
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index b0b569f..d698840 100644 (file)
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -989,11 +989,17 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
         * Ensure a rebooted VM will fault in RAM pages and detect if the
         * guest MMU is turned off and flush the caches as needed.
         *
-        * S2FWB enforces all memory accesses to RAM being cacheable, we
-        * ensure that the cache is always coherent.
+        * S2FWB enforces all memory accesses to RAM being cacheable,
+        * ensuring that the data side is always coherent. We still
+        * need to invalidate the I-cache though, as FWB does *not*
+        * imply CTR_EL0.DIC.
         */
-       if (vcpu->arch.has_run_once && !cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
-               stage2_unmap_vm(vcpu->kvm);
+       if (vcpu->arch.has_run_once) {
+               if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
+                       stage2_unmap_vm(vcpu->kvm);
+               else
+                       __flush_icache_all();
+       }
 
        vcpu_reset_hcr(vcpu);