The NXP Cadence XHCI host has the same issue with Intel's,
it is triggered by reboot test, the test case is described
at this jira ticket.
BuildInfo:
- SCFW
8dcff26, IMX-MKIMAGE
ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
* here that the generic code does not try to make a pci_dev from our
* dev struct in order to setup MSI
*/
- xhci->quirks |= XHCI_PLAT;
+ xhci->quirks |= (XHCI_PLAT | XHCI_CDNS_HOST);
}
static int xhci_cdns3_setup(struct usb_hcd *hcd)
* Without this delay, the subsequent HC register access,
* may result in a system hang very rarely.
*/
- if (xhci->quirks & XHCI_INTEL_HOST)
+ if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_CDNS_HOST))
udelay(1000);
ret = xhci_handshake(&xhci->op_regs->command,
/* Reserved. It was XHCI_U2_DISABLE_WAKE */
#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
#define XHCI_SKIP_ACCESS_RESERVED_REG (1 << 29)
+#define XHCI_CDNS_HOST (1 << 30)
unsigned int num_active_eps;
unsigned int limit_active_eps;