LF-531-1 arm64: dts: imx8mq/imx8mn: fix gpu setting

move gpu device configuration out of soc subsystem,
gpu parameters exceed soc range and will be skipped:
  ranges = <0x0 0x0 0x0 0x3e000000>

Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5d0da2d..9c045b8 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1338,30 +1338,6 @@
                        status = "disabled";
                };
 
-               gpu3d: gpu3d@38000000 {
-                       compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu";
-                       reg = <0x38000000 0x40000>, <0x40000000 0xC0000000>, <0x0 0x10000000>;
-                       reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
-                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "irq_3d";
-                       clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
-                                       <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
-                                       <&clk IMX8MQ_CLK_GPU_AXI>,
-                                       <&clk IMX8MQ_CLK_GPU_AHB>;
-                       clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
-                       assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
-                                               <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
-                                               <&clk IMX8MQ_CLK_GPU_AXI>,
-                                               <&clk IMX8MQ_CLK_GPU_AHB>;
-                       assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
-                                                               <&clk IMX8MQ_GPU_PLL_OUT>,
-                                                               <&clk IMX8MQ_GPU_PLL_OUT>,
-                                                               <&clk IMX8MQ_GPU_PLL_OUT>;
-                       assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>;
-                       power-domains = <&pgc_gpu>;
-                       status = "disabled";
-               };
-
                usb_dwc3_0: usb@38100000 {
                        compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
                        reg = <0x38100000 0x10000>;
@@ -1590,6 +1566,30 @@
                };
        };
 
+       gpu3d: gpu3d@38000000 {
+               compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu";
+               reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>;
+               reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+               interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "irq_3d";
+               clocks =        <&clk IMX8MQ_CLK_GPU_ROOT>,
+                               <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+                               <&clk IMX8MQ_CLK_GPU_AXI>,
+                               <&clk IMX8MQ_CLK_GPU_AHB>;
+               clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
+               assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+                               <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+                               <&clk IMX8MQ_CLK_GPU_AXI>,
+                               <&clk IMX8MQ_CLK_GPU_AHB>;
+               assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+                               <&clk IMX8MQ_GPU_PLL_OUT>,
+                               <&clk IMX8MQ_GPU_PLL_OUT>,
+                               <&clk IMX8MQ_GPU_PLL_OUT>;
+               assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>;
+               power-domains = <&pgc_gpu>;
+               status = "disabled";
+       };
+
        rpmsg: rpmsg{
                compatible = "fsl,imx8mq-rpmsg";
                /* up to now, the following channels are used in imx rpmsg