MLK-17188-2 ARM64: dts: imx8qxp: assign usdhc clock parent

Assign i.MX8QXP uSDHC clocks parent to from PLL1.

This is a workaround for i.MX8QXP usdhc, PLL0 of CONN SS is not
stable sometimes, root cause is still under investigation in
design team. Now change to source from PLL1. Due to PLL1 is
1000MHz, so EMMC HS400ES mode can only work at 166MHz, compare
to the former 198MHz, the performance has small drop, read
performance drop about 10%, write performance drop about 6%.
SD do not has this side effect.

When PLL0 unstable issue is fixed, will change back to use PLL0.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 058f4a6..38567c9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -2356,8 +2356,9 @@
                        <&clk IMX8QXP_SDHC0_CLK>,
                        <&clk IMX8QXP_CLK_DUMMY>;
                clock-names = "ipg", "per", "ahb";
-               assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>;
-               assigned-clock-rates = <400000000>;
+               assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
+               assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+               assigned-clock-rates = <0>, <400000000>;
                power-domains = <&pd_conn_sdch0>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step= <2>;
@@ -2373,8 +2374,9 @@
                        <&clk IMX8QXP_SDHC1_CLK>,
                        <&clk IMX8QXP_CLK_DUMMY>;
                clock-names = "ipg", "per", "ahb";
-               assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>;
-               assigned-clock-rates = <200000000>;
+               assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
+               assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+               assigned-clock-rates = <0>, <200000000>;
                power-domains = <&pd_conn_sdch1>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step= <2>;
@@ -2390,8 +2392,9 @@
                        <&clk IMX8QXP_SDHC2_CLK>,
                        <&clk IMX8QXP_CLK_DUMMY>;
                clock-names = "ipg", "per", "ahb";
-               assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>;
-               assigned-clock-rates = <200000000>;
+               assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
+               assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+               assigned-clock-rates = <0>, <200000000>;
                power-domains = <&pd_conn_sdch2>;
                status = "disabled";
        };