MLK-11556-6 ARM: dts: imx7d-sdb: add epdc support

Add epdc support on i.MX7D SDB board
Since EPDC has pin conflict with ENET1/2, a new DTS file is added.
And EPDC has pin conflict with SIM, so disable SIM by default.

Signed-off-by: Robby Cai <r63905@freescale.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c73a1cc..ee5ac2f 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -457,6 +457,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-nitrogen7.dtb \
        imx7d-sbc-imx7.dtb \
        imx7d-sdb.dtb \
+       imx7d-sdb-epdc.dtb \
        imx7d-sdb-m4.dtb \
        imx7s-colibri-eval-v3.dtb \
        imx7s-warp.dtb \

diff --git a/arch/arm/boot/dts/imx7d-sdb-epdc.dts b/arch/arm/boot/dts/imx7d-sdb-epdc.dts
new file mode 100644 (file)
index 0000000..2cc8045
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-sdb-epdc.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-sdb.dts"
+
+&epdc {
+        status = "okay";
+};
+
+&fec1 {
+       status = "disabled";
+};
+
+&fec2 {
+       status = "disabled";
+};
+
+&max17135 {
+        status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index f9ec45a..6ff0751 100644 (file)
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -235,6 +235,16 @@
        };
 };
 
+&epdc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_epdc0>;
+       V3P3-supply = <&V3P3_reg>;
+       VCOM-supply = <&VCOM_reg>;
+       DISPLAY-supply = <&DISPLAY_reg>;
+       en-gpios = <&gpio_spi 5 0>;
+       status = "disabled";
+};
+
 &epxp {
        status = "okay";
 };
@@ -433,6 +443,76 @@
                reg = <0x39>;
                status = "okay";
        };
+
+       max17135: max17135@48 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_max17135>;
+               compatible = "maxim,max17135";
+               reg = <0x48>;
+               status = "disabled";
+
+               vneg_pwrup = <1>;
+               gvee_pwrup = <2>;
+               vpos_pwrup = <10>;
+               gvdd_pwrup = <12>;
+               gvdd_pwrdn = <1>;
+               vpos_pwrdn = <2>;
+               gvee_pwrdn = <8>;
+               vneg_pwrdn = <10>;
+               gpio_pmic_pwrgood = <&gpio2 31 0>;
+               gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
+               gpio_pmic_wakeup = <&gpio2 23 0>;
+               gpio_pmic_v3p3 = <&gpio2 30 0>;
+               gpio_pmic_intr = <&gpio2 22 0>;
+
+               regulators {
+                       DISPLAY_reg: DISPLAY {
+                               regulator-name = "DISPLAY";
+                       };
+
+                       GVDD_reg: GVDD {
+                               /* 20v */
+                               regulator-name = "GVDD";
+                       };
+
+                       GVEE_reg: GVEE {
+                               /* -22v */
+                               regulator-name = "GVEE";
+                       };
+
+                       HVINN_reg: HVINN {
+                               /* -22v */
+                               regulator-name = "HVINN";
+                       };
+
+                       HVINP_reg: HVINP {
+                               /* 20v */
+                               regulator-name = "HVINP";
+                       };
+
+                       VCOM_reg: VCOM {
+                               regulator-name = "VCOM";
+                               /* 2's-compliment, -4325000 */
+                               regulator-min-microvolt = <0xffbe0178>;
+                               /* 2's-compliment, -500000 */
+                               regulator-max-microvolt = <0xfff85ee0>;
+                       };
+
+                       VNEG_reg: VNEG {
+                               /* -15v */
+                               regulator-name = "VNEG";
+                       };
+
+                       VPOS_reg: VPOS {
+                               /* 15v */
+                               regulator-name = "VPOS";
+                       };
+
+                       V3P3_reg: V3P3 {
+                               regulator-name = "V3P3";
+                       };
+               };
+       };
 };
 
 &i2c4 {
@@ -557,7 +637,7 @@
        pinctrl-0 = <&pinctrl_sim1_1>;
        port = <0>;
        sven_low_active;
-       status = "okay";
+       status = "disabled";
 };
 
 
@@ -703,6 +783,39 @@
                        >;
                };
 
+               pinctrl_epdc0: epdcgrp0 {
+                        fsl,pins = <
+                               MX7D_PAD_EPDC_DATA00__EPDC_DATA0  0x2
+                               MX7D_PAD_EPDC_DATA01__EPDC_DATA1  0x2
+                               MX7D_PAD_EPDC_DATA02__EPDC_DATA2  0x2
+                               MX7D_PAD_EPDC_DATA03__EPDC_DATA3  0x2
+                               MX7D_PAD_EPDC_DATA04__EPDC_DATA4  0x2
+                               MX7D_PAD_EPDC_DATA05__EPDC_DATA5  0x2
+                               MX7D_PAD_EPDC_DATA06__EPDC_DATA6  0x2
+                               MX7D_PAD_EPDC_DATA07__EPDC_DATA7  0x2
+                               MX7D_PAD_EPDC_DATA08__EPDC_DATA8  0x2
+                               MX7D_PAD_EPDC_DATA09__EPDC_DATA9  0x2
+                               MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
+                               MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
+                               MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
+                               MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
+                               MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
+                               MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
+                               MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK   0x2
+                               MX7D_PAD_EPDC_SDLE__EPDC_SDLE     0x2
+                               MX7D_PAD_EPDC_SDOE__EPDC_SDOE     0x2
+                               MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR   0x2
+                               MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0   0x2
+                               MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1   0x2
+                               MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK   0x2
+                               MX7D_PAD_EPDC_GDOE__EPDC_GDOE     0x2
+                               MX7D_PAD_EPDC_GDRL__EPDC_GDRL     0x2
+                               MX7D_PAD_EPDC_GDSP__EPDC_GDSP     0x2
+                               MX7D_PAD_EPDC_BDR0__EPDC_BDR0     0x2
+                               MX7D_PAD_EPDC_BDR1__EPDC_BDR1     0x2
+                        >;
+                };
+
                pinctrl_gpmi_nand_1: gpmi-nand-1 {
                        fsl,pins = <
                                MX7D_PAD_SD3_CLK__NAND_CLE                      0x71
@@ -787,6 +900,16 @@
                        >;
                };
 
+               pinctrl_max17135: max17135grp-1 {
+                       fsl,pins = <
+                               MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x80000000  /* pwrgood */
+                               MX7D_PAD_I2C4_SCL__GPIO4_IO14           0x80000000  /* vcom_ctrl */
+                               MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x80000000  /* wakeup */
+                               MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x80000000  /* v3p3 */
+                               MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x80000000  /* pwr int */
+                       >;
+               };
+
                pinctrl_sai1: sai1grp {
                        fsl,pins = <
                                MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f