MLK-16938 ARM64: dts: imx8: refine the imx8 dts

- Add the clk_req property for imx8 pcie, make sure that
the clk_req would be active.
- Correct the spell mistake of pcie pinctrl on imx8qxp.
- Fix the potential conflication with the usage of SC MU,
remove the useless "fsl,imx8-mu" of rpmsg.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

diff --git a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
index d51250a..bd2bd23 100644 (file)
--- a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
+++ b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
@@ -17,7 +17,7 @@ message unit module for RPMSG
 
 - mu_rpmsg : The message unit module used to do the communications
   between the asymmetric cores.
-- compatible : "fsl,imx8-mu", "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1".
+- compatible : "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1".
   Different mu module would be used by the different remote processor.
   The "fsl, imx6sx-mu" is used by the first remote processor.
   The "fsl,imx-mu-rpmsg1" is used by the second remote process.
@@ -46,7 +46,7 @@ imx_rpmsg: imx_rpmsg {
        ranges;
 
        mu_rpmsg: mu_rpmsg@37440000 {
-               compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
+               compatible = "fsl,imx6sx-mu";
                reg = <0x0 0x37440000 0x0 0x10000>;
                interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-parent = <&intmux_cm40>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index b4f5263..caccbf7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -902,6 +902,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pciea>;
        reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+       clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
 
@@ -910,6 +911,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcieb>;
        reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>;
+       clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
        epdev_on-supply = <&epdev_on>;
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 02a67d7..5ab767d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -713,6 +713,7 @@
        pinctrl-0 = <&pinctrl_pciea>;
        disable-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
        reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+       clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
        epdev_on-supply = <&epdev_on>;
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 527413e..9e2e1cd 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -3182,7 +3182,7 @@
                ranges;
 
                mu_rpmsg: mu_rpmsg@37440000 {
-                       compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
+                       compatible = "fsl,imx6sx-mu";
                        reg = <0x0 0x37440000 0x0 0x10000>;
                        interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-parent = <&intmux_cm40>;
@@ -3198,7 +3198,7 @@
                };
 
                mu_rpmsg1: mu_rpmsg1@3b440000 {
-                       compatible = "fsl,imx8-mu", "fsl,imx-mu-rpmsg1";
+                       compatible = "fsl,imx-mu-rpmsg1";
                        reg = <0x0 0x3b440000 0x0 0x10000>;
                        interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-parent = <&intmux_cm41>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 15e64f3..a7acc45 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -427,7 +427,7 @@
                        >;
                };
 
-               pinctrl_pcieb: pcieagrp{
+               pinctrl_pcieb: pciebgrp{
                        fsl,pins = <
                                SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00         0x06000021
                                SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01        0x06000021
@@ -706,6 +706,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcieb>;
        reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
+       clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 47b033f..33b9fbf 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -2412,7 +2412,7 @@
                ranges;
 
                mu_rpmsg: mu_rpmsg@37440000 {
-                       compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
+                       compatible = "fsl,imx6sx-mu";
                        reg = <0x0 0x37440000 0x0 0x10000>;
                        interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-parent = <&intmux_cm40>;