#define SC_RPC_H
/* Note: Check SCFW API Released DOC before you want to modify something */
+/* Defines */
+
+#define SCFW_API_VERSION_MAJOR 1U
+#define SCFW_API_VERSION_MINOR 13U
+
#define SC_RPC_VERSION 1U
#define SC_RPC_MAX_MSG 8U
#define PM_FUNC_SET_SYS_POWER_MODE 19U
#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
#define PM_FUNC_GET_SYS_POWER_MODE 2U
+#define PM_FUNC_PARTITION_WAKE 28U
#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U
#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U
#define PM_FUNC_REQ_LOW_POWER_MODE 16U
#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
#define PM_FUNC_GET_CLOCK_PARENT 15U
#define PM_FUNC_RESET 13U
#define PM_FUNC_RESET_REASON 10U
+#define PM_FUNC_GET_RESET_PART 26U
#define PM_FUNC_BOOT 8U
+#define PM_FUNC_SET_BOOT_PARM 27U
#define PM_FUNC_REBOOT 9U
#define PM_FUNC_REBOOT_PARTITION 12U
+#define PM_FUNC_REBOOT_CONTINUE 25U
#define PM_FUNC_CPU_START 11U
+#define PM_FUNC_CPU_RESET 23U
#define PM_FUNC_IS_PARTITION_STARTED 24U
/* MISC RPC */
#define MISC_FUNC_GET_CONTROL 2U
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U
#define MISC_FUNC_SET_DMA_GROUP 5U
-#define MISC_FUNC_SECO_IMAGE_LOAD 8U
-#define MISC_FUNC_SECO_AUTHENTICATE 9U
-#define MISC_FUNC_SECO_FUSE_WRITE 20U
-#define MISC_FUNC_SECO_ENABLE_DEBUG 21U
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U
-#define MISC_FUNC_SECO_BUILD_INFO 24U
#define MISC_FUNC_DEBUG_OUT 10U
#define MISC_FUNC_WAVEFORM_CAPTURE 6U
#define MISC_FUNC_BUILD_INFO 15U
+#define MISC_FUNC_API_VER 35U
#define MISC_FUNC_UNIQUE_ID 19U
#define MISC_FUNC_SET_ARI 3U
#define MISC_FUNC_BOOT_STATUS 7U
#define MISC_FUNC_SET_TEMP 12U
#define MISC_FUNC_GET_TEMP 13U
#define MISC_FUNC_GET_BOOT_DEV 16U
+#define MISC_FUNC_GET_BOOT_TYPE 33U
+#define MISC_FUNC_GET_BOOT_CONTAINER 36U
#define MISC_FUNC_GET_BUTTON_STATUS 18U
+#define MISC_FUNC_ROMPATCH_CHECKSUM 26U
+#define MISC_FUNC_BOARD_IOCTL 34U
/* PAD RPC */
#define PAD_FUNC_UNKNOWN 0
#define RM_FUNC_GET_RESOURCE_INFO 16U
#define RM_FUNC_MEMREG_ALLOC 17U
#define RM_FUNC_MEMREG_SPLIT 29U
+#define RM_FUNC_MEMREG_FRAG 32U
#define RM_FUNC_MEMREG_FREE 18U
#define RM_FUNC_FIND_MEMREG 30U
#define RM_FUNC_ASSIGN_MEMREG 19U
#define RM_FUNC_DUMP 27U
/* SECO RPC */
-#define SECO_FUNC_UNKNOWN 0 /*!< Unknown function */
-#define SECO_FUNC_IMAGE_LOAD 1U /*!< Index for seco_image_load() RPC call */
-#define SECO_FUNC_AUTHENTICATE 2U /*!< Index for seco_authenticate() RPC call */
-#define SECO_FUNC_FORWARD_LIFECYCLE 3U /*!< Index for seco_forward_lifecycle() RPC call */
-#define SECO_FUNC_RETURN_LIFECYCLE 4U /*!< Index for seco_return_lifecycle() RPC call */
-#define SECO_FUNC_COMMIT 5U /*!< Index for seco_commit() RPC call */
-#define SECO_FUNC_ATTEST_MODE 6U /*!< Index for seco_attest_mode() RPC call */
-#define SECO_FUNC_ATTEST 7U /*!< Index for seco_attest() RPC call */
-#define SECO_FUNC_GET_ATTEST_PKEY 8U /*!< Index for seco_get_attest_pkey() RPC call */
-#define SECO_FUNC_GET_ATTEST_SIGN 9U /*!< Index for seco_get_attest_sign() RPC call */
-#define SECO_FUNC_ATTEST_VERIFY 10U /*!< Index for seco_attest_verify() RPC call */
-#define SECO_FUNC_GEN_KEY_BLOB 11U /*!< Index for seco_gen_key_blob() RPC call */
-#define SECO_FUNC_LOAD_KEY 12U /*!< Index for seco_load_key() RPC call */
-#define SECO_FUNC_GET_MP_KEY 13U /*!< Index for seco_get_mp_key() RPC call */
-#define SECO_FUNC_UPDATE_MPMR 14U /*!< Index for seco_update_mpmr() RPC call */
-#define SECO_FUNC_GET_MP_SIGN 15U /*!< Index for seco_get_mp_sign() RPC call */
-#define SECO_FUNC_BUILD_INFO 16U /*!< Index for seco_build_info() RPC call */
-#define SECO_FUNC_CHIP_INFO 17U /*!< Index for seco_chip_info() RPC call */
-#define SECO_FUNC_ENABLE_DEBUG 18U /*!< Index for seco_enable_debug() RPC call */
-#define SECO_FUNC_GET_EVENT 19U /*!< Index for seco_get_event() RPC call */
-#define SECO_FUNC_FUSE_WRITE 20U /*!< Index for seco_fuse_write() RPC call */
+#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
+#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
+#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
+#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
+#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
+#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
+#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
+#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
+#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
+#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
+#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
+#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
+#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
+#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
+#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
+#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
+#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
+#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
+#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
+#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
+#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
+#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
+#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
+#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
+#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
+#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
+
+/* IRQ RPC */
+#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
+#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
+#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
+
+/* TIMER RPC */
+#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
#endif /* SC_RPC_H */
#include <asm/arch/sci/svc/pm/api.h>
#include <asm/arch/sci/svc/rm/api.h>
#include <asm/arch/sci/svc/seco/api.h>
+#include <asm/arch/sci/svc/irq/api.h>
+#include <asm/arch/sci/svc/timer/api.h>
#include <asm/arch/sci/rpc.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <linux/errno.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef SC_IRQ_API_H
+#define SC_IRQ_API_H
+
+/* Defines */
+
+#define SC_IRQ_NUM_GROUP 7U /* Number of groups */
+
+/* Defines for sc_irq_group_t */
+#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */
+#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */
+#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */
+#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */
+#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */
+#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */
+#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */
+
+/* Defines for sc_irq_temp_t */
+#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */
+
+/* Defines for sc_irq_wdog_t */
+#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */
+
+/* Defines for sc_irq_rtc_t */
+#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */
+
+/* Defines for sc_irq_wake_t */
+#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */
+#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */
+#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */
+#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */
+#define SC_IRQ_BC_PAD (1U << 4U) /* Pad wakeup (broadcast to all partitions) */
+#define SC_IRQ_SW_WAKE (1U << 5U) /* Software requested wake */
+#define SC_IRQ_SECVIO (1U << 6U) /* Security violation */
+
+/* Defines for sc_irq_sysctr_t */
+#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */
+
+/* Types */
+
+/*
+ * This type is used to declare an interrupt group.
+ */
+typedef u8 sc_irq_group_t;
+
+/*
+ * This type is used to declare a bit mask of temp interrupts.
+ */
+typedef u8 sc_irq_temp_t;
+
+/*
+ * This type is used to declare a bit mask of watchdog interrupts.
+ */
+typedef u8 sc_irq_wdog_t;
+
+/*
+ * This type is used to declare a bit mask of RTC interrupts.
+ */
+typedef u8 sc_irq_rtc_t;
+
+/*
+ * This type is used to declare a bit mask of wakeup interrupts.
+ */
+typedef u8 sc_irq_wake_t;
+
+#endif /* SC_IRQ_API_H */
#ifndef SC_MISC_API_H
#define SC_MISC_API_H
+/* Defines for type widths */
+#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */
+/* Max DMA channel priority group */
+#define SC_MISC_DMA_GRP_MAX 31U
/* Defines for sc_misc_boot_status_t */
#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */
-
/* Defines for sc_misc_temp_t */
-#define SC_MISC_TEMP 0U /* Temp sensor */
-#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
-#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
+#define SC_MISC_TEMP 0U /* Temp sensor */
+#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
+#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
+
+/* Defines for sc_misc_bt_t */
+#define SC_MISC_BT_PRIMARY 0U /* Primary boot */
+#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */
+#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */
+#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */
+#define SC_MISC_BT_SERIAL 4U /* Serial boot */
+/* Types */
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
-#define SC_MISC_REL_CONTAINER 2U /* Release container */
+/*
+ * This type is used to store a DMA channel priority group.
+ */
+typedef u8 sc_misc_dma_group_t;
+/*
+ * This type is used report boot status.
+ */
typedef u8 sc_misc_boot_status_t;
+/*
+ * This type is used report boot status.
+ */
typedef u8 sc_misc_temp_t;
+/*
+ * This type is used report the boot type.
+ */
+typedef u8 sc_misc_bt_t;
#endif /* SC_MISC_API_H */
#ifndef SC_PM_API_H
#define SC_PM_API_H
+#include <asm/arch/sci/types.h>
+/* Defines for type widths */
+#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */
+/* Defines for ALL parameters */
+#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */
/* Defines for sc_pm_power_mode_t */
#define SC_PM_PW_MODE_OFF 0U /* Power off */
#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */
#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */
+/* Defines for sc_pm_reset_type_t */
+#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
+
+/* Defines for sc_pm_reset_reason_t */
+#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
+#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */
+#define SC_PM_RESET_REASON_SW 2U /* Software reset */
+#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */
+#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */
+#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */
+#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */
+#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */
+#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */
+#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */
+#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */
+#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */
+
+/* Defines for sc_pm_sys_if_t */
+#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
+#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
+
+/* Defines for sc_pm_wake_src_t */
+#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
+#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
+/* Types */
+
+/*
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
typedef u8 sc_pm_power_mode_t;
+
+/*
+ * This type is used to declare a clock.
+ */
typedef u8 sc_pm_clk_t;
+
+/*
+ * This type is used to declare a clock mode.
+ */
typedef u8 sc_pm_clk_mode_t;
+
+/*
+ * This type is used to declare the clock parent.
+ */
typedef u8 sc_pm_clk_parent_t;
+
+/*
+ * This type is used to declare clock rates.
+ */
typedef u32 sc_pm_clock_rate_t;
+/*
+ * This type is used to declare a desired reset type.
+ */
+typedef u8 sc_pm_reset_type_t;
+
+/*
+ * This type is used to declare a reason for a reset.
+ */
+typedef u8 sc_pm_reset_reason_t;
+
+/*
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef u8 sc_pm_sys_if_t;
+
+/*
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef u8 sc_pm_wake_src_t;
#endif /* SC_PM_API_H */
/* Types */
-/*!
+/*
* This type is used to declare a resource partition.
*/
typedef u8 sc_rm_pt_t;
-/*!
+/*
* This type is used to declare a memory region.
*/
typedef u8 sc_rm_mr_t;
-/*!
+/*
* This type is used to declare a resource domain ID used by the
* isolation HW.
*/
typedef u8 sc_rm_did_t;
-/*!
+/*
* This type is used to declare an SMMU StreamID.
*/
typedef u16 sc_rm_sid_t;
-/*!
+/*
* This type is a used to declare master transaction attributes.
*/
typedef u8 sc_rm_spa_t;
+/*
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
typedef u8 sc_rm_perm_t;
#endif /* SC_RM_API_H */
#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */
#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */
#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */
+#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */
#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */
#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */
/* Types */
-/*!
+/*
* This type is used to issue SECO authenticate commands.
*/
typedef uint8_t sc_seco_auth_cmd_t;
-/*!
+/*
* This type is used to return the RNG initialization status.
*/
typedef uint32_t sc_seco_rng_stat_t;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
+
+/* Defines */
+
+/* Defines for type widths */
+#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */
+
+/* Defines for sc_timer_wdog_action_t */
+#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */
+
+/* Types */
+
+/*
+ * This type is used to configure the watchdog action.
+ */
+typedef u8 sc_timer_wdog_action_t;
+
+/*
+ * This type is used to declare a watchdog time value in milliseconds.
+ */
+typedef u32 sc_timer_wdog_time_t;
+
+#endif /* SC_TIMER_API_H */
/* Defines for common frequencies */
#define SC_32KHZ 32768U /* 32KHz */
#define SC_10MHZ 10000000U /* 10MHz */
+#define SC_16MHZ 16000000U /* 16MHz */
#define SC_20MHZ 20000000U /* 20MHz */
#define SC_25MHZ 25000000U /* 25MHz */
#define SC_27MHZ 27000000U /* 27MHz */
#define SC_594MHZ 594000000U /* 594MHz */
#define SC_625MHZ 625000000U /* 625MHz */
#define SC_640MHZ 640000000U /* 640MHz */
+#define SC_648MHZ 648000000U /* 648MHz */
#define SC_650MHZ 650000000U /* 650MHz */
#define SC_667MHZ 666666667U /* 667MHz */
#define SC_675MHZ 675000000U /* 675MHz */
#define SC_700MHZ 700000000U /* 700MHz */
#define SC_720MHZ 720000000U /* 720MHz */
#define SC_750MHZ 750000000U /* 750MHz */
+#define SC_753MHZ 753000000U /* 753MHz */
+#define SC_793MHZ 793000000U /* 793MHz */
#define SC_800MHZ 800000000U /* 800MHz */
#define SC_850MHZ 850000000U /* 850MHz */
+#define SC_858MHZ 858000000U /* 858MHz */
#define SC_900MHZ 900000000U /* 900MHz */
+#define SC_953MHZ 953000000U /* 953MHz */
+#define SC_963MHZ 963000000U /* 963MHz */
#define SC_1000MHZ 1000000000U /* 1GHz */
#define SC_1060MHZ 1060000000U /* 1.06GHz */
+#define SC_1068MHZ 1068000000U /* 1.068GHz */
+#define SC_1121MHZ 1121000000U /* 1.121GHz */
+#define SC_1173MHZ 1173000000U /* 1.173GHz */
#define SC_1188MHZ 1188000000U /* 1.188GHz */
#define SC_1260MHZ 1260000000U /* 1.26GHz */
+#define SC_1278MHZ 1278000000U /* 1.278GHz */
#define SC_1280MHZ 1280000000U /* 1.28GHz */
#define SC_1300MHZ 1300000000U /* 1.3GHz */
+#define SC_1313MHZ 1313000000U /* 1.313GHz */
+#define SC_1345MHZ 1345000000U /* 1.345GHz */
#define SC_1400MHZ 1400000000U /* 1.4GHz */
#define SC_1500MHZ 1500000000U /* 1.5GHz */
#define SC_1600MHZ 1600000000U /* 1.6GHz */
#define SC_755MHZ 755250000U /* 755.25MHz */
/* Defines for type widths */
-#define SC_FADDR_W 36U /* Width of sc_faddr_t */
#define SC_BOOL_W 1U /* Width of sc_bool_t */
#define SC_ERR_W 4U /* Width of sc_err_t */
#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
#define SC_C_IPG_STOP_MODE 53U
#define SC_C_IPG_STOP_ACK 54U
#define SC_C_SYNC_CTRL 55U
-#define SC_C_LAST 56U
+#define SC_C_OFS_AUDIO_ALT 56U
+#define SC_C_DSP_BYP 57U
+#define SC_C_LAST 58U
#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
* Copyright 2018 NXP
*/
-#ifndef _SC_PADS_H
-#define _SC_PADS_H
+#ifndef SC_PADS_H
+#define SC_PADS_H
#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
-#endif /* _SC_PADS_H */
+/* Fake Pad Mux Definitions */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0
+#endif /* SC_PADS_H */
#define SC_R_DC_0_BLIT2 21
#define SC_R_DC_0_BLIT_OUT 22
#define SC_R_PERF 23
-#define SC_R_UNUSED5 24
+#define SC_R_USB_1_PHY 24
#define SC_R_DC_0_WARP 25
-#define SC_R_UNUSED7 26
-#define SC_R_UNUSED8 27
+#define SC_R_V2X_MU_0 26
+#define SC_R_V2X_MU_1 27
#define SC_R_DC_0_VIDEO0 28
#define SC_R_DC_0_VIDEO1 29
#define SC_R_DC_0_FRAC0 30
-#define SC_R_UNUSED6 31
+#define SC_R_V2X_MU_2 31
#define SC_R_DC_0 32
#define SC_R_GPU_2_PID0 33
#define SC_R_DC_0_PLL_0 34
#define SC_R_DC_1_BLIT1 37
#define SC_R_DC_1_BLIT2 38
#define SC_R_DC_1_BLIT_OUT 39
-#define SC_R_UNUSED9 40
-#define SC_R_UNUSED10 41
+#define SC_R_V2X_MU_3 40
+#define SC_R_V2X_MU_4 41
#define SC_R_DC_1_WARP 42
-#define SC_R_UNUSED11 43
-#define SC_R_UNUSED12 44
+#define SC_R_TBU_CTL 43
+#define SC_R_SECVIO 44
#define SC_R_DC_1_VIDEO0 45
#define SC_R_DC_1_VIDEO1 46
#define SC_R_DC_1_FRAC0 47
#define SC_R_DMA_1_CH29 137
#define SC_R_DMA_1_CH30 138
#define SC_R_DMA_1_CH31 139
-#define SC_R_UNUSED1 140
-#define SC_R_UNUSED2 141
-#define SC_R_UNUSED3 142
-#define SC_R_UNUSED4 143
+#define SC_R_V2X_PID0 140
+#define SC_R_V2X_PID1 141
+#define SC_R_V2X_PID2 142
+#define SC_R_V2X_PID3 143
#define SC_R_GPU_0_PID0 144
#define SC_R_GPU_0_PID1 145
#define SC_R_GPU_0_PID2 146
#define SC_R_M4_0_UART 287
#define SC_R_M4_0_I2C 288
#define SC_R_M4_0_INTMUX 289
-#define SC_R_UNUSED15 290
-#define SC_R_UNUSED16 291
+#define SC_R_ENET_0_A0 290
+#define SC_R_ENET_0_A1 291
#define SC_R_M4_0_MU_0B 292
#define SC_R_M4_0_MU_0A0 293
#define SC_R_M4_0_MU_0A1 294
#define SC_R_VPU_PID5 363
#define SC_R_VPU_PID6 364
#define SC_R_VPU_PID7 365
-#define SC_R_VPU_UART 366
-#define SC_R_VPUCORE 367
-#define SC_R_VPUCORE_0 368
-#define SC_R_VPUCORE_1 369
-#define SC_R_VPUCORE_2 370
-#define SC_R_VPUCORE_3 371
+#define SC_R_ENET_0_A2 366
+#define SC_R_ENET_1_A0 367
+#define SC_R_ENET_1_A1 368
+#define SC_R_ENET_1_A2 369
+#define SC_R_ENET_1_A3 370
+#define SC_R_ENET_1_A4 371
#define SC_R_DMA_4_CH0 372
#define SC_R_DMA_4_CH1 373
#define SC_R_DMA_4_CH2 374
#define SC_R_DMA_5_CH3 544
#define SC_R_ATTESTATION 545
#define SC_R_LAST 546
-
#define SC_R_NONE 0xFFF0
#endif /* DT_BINDINGS_RSCRC_IMX_H */
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