MLK-17158-3 arm64: dts: imx8mq: Add a RAWNAND dedicated DTS for ARM2

Add fsl-imx8mq-ddr4-arm2-gpmi-nand.dts which enables the RAWNAND on
i.MX8MQ DDR4 ARM2 board.

Signed-off-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 03691d9..58cb1aa 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
                                  fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dtb
 dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
                                 fsl-imx8mq-ddr4-arm2.dtb \
+                                fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \
                                 fsl-imx8mq-evk.dtb \
                                 fsl-imx8mq-evk-m4.dtb \
                                 fsl-imx8mq-evk-pcie1-m2.dtb \

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts
new file mode 100644 (file)
index 0000000..bc6c8b7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 NXP
+ *
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ */
+
+#include "fsl-imx8mq-ddr4-arm2.dts"
+
+&iomuxc {
+       imx8mq-arm2 {
+               pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE               0x00000096
+                               MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B           0x00000096
+                               MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE               0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06         0x00000096
+                               MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07         0x00000096
+                               MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B             0x00000096
+                               MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B       0x00000056
+                               MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B             0x00000096
+                               MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B             0x00000096
+                       >;
+               };
+       };
+};
+
+&gpmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+       status = "okay";
+       nand-on-flash-bbt;
+};