We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit
fd8fbf7fa0b10199ac89cd13cae851149f51accb)
ret = enable_fec_anatop_clock(0, ENET_125MHZ);
if (ret)
printf("Error fec anatop clock settings!\n");
-
- setup_iomux_enet();
}
int board_eth_init(bd_t *bis)
{
- setup_fec();
+ setup_iomux_enet();
return cpu_eth_init(bis);
}
#ifdef CONFIG_MTD_NOR_FLASH
setup_iomux_eimnor();
#endif
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
return 0;
}
return 1;
}
-int board_eth_init(bd_t *bis)
+static void setup_fec(void)
{
if (is_mx6dqp()) {
int ret;
if (ret)
printf("Error fec anatop clock settings!\n");
}
+}
+int board_eth_init(bd_t *bis)
+{
setup_iomux_enet();
return cpu_eth_init(bis);
setup_sata();
#endif
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
return 0;
}