arm64: Move post_ttbr_update_workaround to C code

commit 95e3de3590e3 upstream.

We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
Conflicts:
	don't include PAN related changes
	arch/arm64/include/asm/assembler.h
	arch/arm64/kernel/entry.S
	arch/arm64/mm/proc.S

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index f00f5ee..b9b0875 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -233,6 +233,15 @@ switch_mm_fastpath:
        cpu_switch_mm(mm->pgd, mm);
 }
 
+/* Errata workaround post TTBRx_EL1 update. */
+asmlinkage void post_ttbr_update_workaround(void)
+{
+       asm(ALTERNATIVE("nop; nop; nop",
+                       "ic iallu; dsb nsh; isb",
+                       ARM64_WORKAROUND_CAVIUM_27456,
+                       CONFIG_CAVIUM_ERRATUM_27456));
+}
+
 static int asids_init(void)
 {
        asid_bits = get_cpu_asid_bits();

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 135a698..619da1c 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm)
        isb
        msr     ttbr0_el1, x0                   // now update TTBR0
        isb
-       post_ttbr0_update_workaround
-       ret
+       b       post_ttbr_update_workaround     // Back to C code...
 ENDPROC(cpu_do_switch_mm)
 
        .pushsection ".idmap.text", "awx"