fsl-imx8mm-evk.dtb \
fsl-imx8mm-ddr3l-val.dtb \
fsl-imx8mm-ddr4-evk.dtb \
- fsl-imx8mm-ddr4-val.dtb
+ fsl-imx8mm-ddr4-val.dtb \
fsl-imx8mm-evk.dtb \
fsl-imx8mn-ddr4-evk.dtb
bool "imx8mm DDR4 EVK board"
select IMX8MM
select IMX8M_DDR4
+
+config TARGET_IMX8MN_EVK
+ bool "imx8mn DDR4 EVK board"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR4
+
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mq_arm2/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mm_val/Kconfig"
+source "board/freescale/imx8mn_evk/Kconfig"
endif
--- /dev/null
+if TARGET_IMX8MN_EVK
+
+config SYS_BOARD
+ default "imx8mn_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_evk"
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mn_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
--- /dev/null
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x3d400000,0x81040010},
+ {0x3d400030,0x00000020},
+ {0x3d400034,0x00221306},
+ {0x3d400050,0x00210070},
+ {0x3d400054,0x00010008},
+ {0x3d400060,0x00000000},
+ {0x3d400064,0x0092014a},
+ {0x3d4000c0,0x00000000},
+ {0x3d4000c4,0x00001000},
+ {0x3d4000d0,0xc0030126},
+ {0x3d4000d4,0x00770000},
+ {0x3d4000dc,0x08340105},
+ {0x3d4000e0,0x00180200},
+ {0x3d4000e4,0x00110000},
+ {0x3d4000e8,0x02000740},
+ {0x3d4000ec,0x00000850},
+ {0x3d4000f4,0x00000ec7},
+ {0x3d400100,0x11122914},
+ {0x3d400104,0x0004051c},
+ {0x3d400108,0x0608050d},
+ {0x3d40010c,0x0000400c},
+ {0x3d400110,0x08030409},
+ {0x3d400114,0x06060403},
+ {0x3d40011c,0x00000606},
+ {0x3d400120,0x07070d0c},
+ {0x3d400124,0x0002040a},
+ {0x3d40012c,0x1809010e},
+ {0x3d400130,0x00000008},
+ {0x3d40013c,0x00000000},
+ {0x3d400180,0x01000040},
+ {0x3d400184,0x0000493e},
+ {0x3d400190,0x038b8207},
+ {0x3d400194,0x02020303},
+ {0x3d400198,0x07f04011},
+ {0x3d40019c,0x000000b0},
+ {0x3d4001a0,0xe0400018},
+ {0x3d4001a4,0x0048005a},
+ {0x3d4001a8,0x80000000},
+ {0x3d4001b0,0x00000001},
+ {0x3d4001b4,0x00000b07},
+ {0x3d4001b8,0x00000004},
+ {0x3d4001c0,0x00000001},
+ {0x3d4001c4,0x00000000},
+ {0x3d400240,0x06000610},
+ {0x3d400244,0x00001323},
+ {0x3d400200,0x00003f1f},
+ {0x3d400204,0x003f0909},
+ {0x3d400208,0x01010100},
+ {0x3d40020c,0x01010101},
+ {0x3d400210,0x00001f1f},
+ {0x3d400214,0x07070707},
+ {0x3d400218,0x07070707},
+ {0x3d40021c,0x00000f07},
+ {0x3d400220,0x00003f01},
+ {0x3d402050,0x00210070},
+ {0x3d402064,0x00180037},
+ {0x3d4020dc,0x00000105},
+ {0x3d4020e0,0x00000000},
+ {0x3d4020e8,0x02000740},
+ {0x3d4020ec,0x00000050},
+ {0x3d402100,0x08030604},
+ {0x3d402104,0x00020205},
+ {0x3d402108,0x05050309},
+ {0x3d40210c,0x0000400c},
+ {0x3d402110,0x02030202},
+ {0x3d402114,0x03030202},
+ {0x3d402118,0x0a070008},
+ {0x3d40211c,0x00000d09},
+ {0x3d402120,0x08084b09},
+ {0x3d402124,0x00020308},
+ {0x3d402128,0x000f0d06},
+ {0x3d40212c,0x12060111},
+ {0x3d402130,0x00000008},
+ {0x3d40213c,0x00000000},
+ {0x3d402180,0x01000040},
+ {0x3d402190,0x03848204},
+ {0x3d402194,0x02020303},
+ {0x3d4021b4,0x00000404},
+ {0x3d4021b8,0x00000004},
+ {0x3d402240,0x07000600},
+ {0x3d403050,0x00210070},
+ {0x3d403064,0x0006000d},
+ {0x3d4030dc,0x00000105},
+ {0x3d4030e0,0x00000000},
+ {0x3d4030e8,0x02000740},
+ {0x3d4030ec,0x00000050},
+ {0x3d403100,0x07010101},
+ {0x3d403104,0x00020202},
+ {0x3d403108,0x05050309},
+ {0x3d40310c,0x0000400c},
+ {0x3d403110,0x01030201},
+ {0x3d403114,0x03030202},
+ {0x3d40311c,0x00000303},
+ {0x3d403120,0x02020d02},
+ {0x3d403124,0x00020208},
+ {0x3d403128,0x000f0d06},
+ {0x3d40312c,0x0e02010e},
+ {0x3d403130,0x00000008},
+ {0x3d40313c,0x00000000},
+ {0x3d403180,0x01000040},
+ {0x3d403190,0x03848204},
+ {0x3d403194,0x02020303},
+ {0x3d4031b4,0x00000404},
+ {0x3d4031b8,0x00000004},
+ {0x3d403240,0x07000600},
+ {0x3d400400,0x00000100},
+ {0x3d400250,0x317d1a07},
+ {0x3d400254,0x0000000f},
+ {0x3d40025c,0x2a001b76},
+ {0x3d400264,0x7300b473},
+ {0x3d40026c,0x30000e06},
+ {0x3d400300,0x00000014},
+ {0x3d40036c,0x00000010},
+ {0x3d400404,0x00013193},
+ {0x3d400408,0x00006096},
+ {0x3d400490,0x00000001},
+ {0x3d400494,0x02000c00},
+ {0x3d400498,0x003c00db},
+ {0x3d40049c,0x00100009},
+ {0x3d4004a0,0x00000002},
+
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x0001005f,0x000002fd},
+ {0x0001015f,0x000002fd},
+ {0x0001105f,0x000002fd},
+ {0x0001115f,0x000002fd},
+ {0x0011005f,0x000002fd},
+ {0x0011015f,0x000002fd},
+ {0x0011105f,0x000002fd},
+ {0x0011115f,0x000002fd},
+ {0x0021005f,0x000002fd},
+ {0x0021015f,0x000002fd},
+ {0x0021105f,0x000002fd},
+ {0x0021115f,0x000002fd},
+ {0x00000055,0x00000355},
+ {0x00001055,0x00000355},
+ {0x00002055,0x00000355},
+ {0x00003055,0x00000355},
+ {0x00004055,0x00000055},
+ {0x00005055,0x00000055},
+ {0x00006055,0x00000355},
+ {0x00007055,0x00000355},
+ {0x00008055,0x00000355},
+ {0x00009055,0x00000355},
+ {0x000200c5,0x0000000a},
+ {0x001200c5,0x00000007},
+ {0x002200c5,0x00000007},
+ {0x0002002e,0x00000002},
+ {0x0012002e,0x00000002},
+ {0x0022002e,0x00000002},
+ {0x00020024,0x00000008},
+ {0x0002003a,0x00000002},
+ {0x0002007d,0x00000212},
+ {0x0002007c,0x00000061},
+ {0x00120024,0x00000008},
+ {0x0002003a,0x00000002},
+ {0x0012007d,0x00000212},
+ {0x0012007c,0x00000061},
+ {0x00220024,0x00000008},
+ {0x0002003a,0x00000002},
+ {0x0022007d,0x00000212},
+ {0x0022007c,0x00000061},
+ {0x00020056,0x00000006},
+ {0x00120056,0x0000000a},
+ {0x00220056,0x0000000a},
+ {0x0001004d,0x0000001a},
+ {0x0001014d,0x0000001a},
+ {0x0001104d,0x0000001a},
+ {0x0001114d,0x0000001a},
+ {0x0011004d,0x0000001a},
+ {0x0011014d,0x0000001a},
+ {0x0011104d,0x0000001a},
+ {0x0011114d,0x0000001a},
+ {0x0021004d,0x0000001a},
+ {0x0021014d,0x0000001a},
+ {0x0021104d,0x0000001a},
+ {0x0021114d,0x0000001a},
+ {0x00010049,0x00000e38},
+ {0x00010149,0x00000e38},
+ {0x00011049,0x00000e38},
+ {0x00011149,0x00000e38},
+ {0x00110049,0x00000e38},
+ {0x00110149,0x00000e38},
+ {0x00111049,0x00000e38},
+ {0x00111149,0x00000e38},
+ {0x00210049,0x00000e38},
+ {0x00210149,0x00000e38},
+ {0x00211049,0x00000e38},
+ {0x00211149,0x00000e38},
+ {0x00000043,0x00000063},
+ {0x00001043,0x00000063},
+ {0x00002043,0x00000063},
+ {0x00003043,0x00000063},
+ {0x00004043,0x00000063},
+ {0x00005043,0x00000063},
+ {0x00006043,0x00000063},
+ {0x00007043,0x00000063},
+ {0x00008043,0x00000063},
+ {0x00009043,0x00000063},
+ {0x00020018,0x00000001},
+ {0x00020075,0x00000002},
+ {0x00020050,0x00000000},
+ {0x00020008,0x00000258},
+ {0x00120008,0x00000064},
+ {0x00220008,0x00000019},
+ {0x00020088,0x00000009},
+ {0x000200b2,0x00000268},
+ {0x00010043,0x000005b1},
+ {0x00010143,0x000005b1},
+ {0x00011043,0x000005b1},
+ {0x00011143,0x000005b1},
+ {0x001200b2,0x00000268},
+ {0x00110043,0x000005b1},
+ {0x00110143,0x000005b1},
+ {0x00111043,0x000005b1},
+ {0x00111143,0x000005b1},
+ {0x002200b2,0x00000268},
+ {0x00210043,0x000005b1},
+ {0x00210143,0x000005b1},
+ {0x00211043,0x000005b1},
+ {0x00211143,0x000005b1},
+ {0x0002005b,0x00007529},
+ {0x0002005c,0x00000000},
+ {0x000200fa,0x00000001},
+ {0x001200fa,0x00000001},
+ {0x002200fa,0x00000001},
+ {0x00020019,0x00000005},
+ {0x00120019,0x00000005},
+ {0x00220019,0x00000005},
+ {0x000200f0,0x00005665},
+ {0x000200f1,0x00005555},
+ {0x000200f2,0x00005555},
+ {0x000200f3,0x00005555},
+ {0x000200f4,0x00005555},
+ {0x000200f5,0x00005555},
+ {0x000200f6,0x00005555},
+ {0x000200f7,0x0000f000},
+ {0x0001004a,0x00000500},
+ {0x0001104a,0x00000500},
+ {0x00020025,0x00000000},
+ {0x0002002d,0x00000000},
+ {0x0012002d,0x00000000},
+ {0x0022002d,0x00000000},
+ {0x0002002c,0x00000000},
+ {0x000200c7,0x00000021},
+ {0x000200ca,0x00000024},
+ {0x000200cc,0x000001f7},
+ {0x001200c7,0x00000021},
+ {0x001200ca,0x00000024},
+ {0x001200cc,0x000001f7},
+ {0x002200c7,0x00000021},
+ {0x002200ca,0x00000024},
+ {0x002200cc,0x000001f7},
+
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2,0x0},
+ {0x1200b2,0x0},
+ {0x2200b2,0x0},
+ {0x0200cb,0x0},
+ {0x010043,0x0},
+ {0x110043,0x0},
+ {0x210043,0x0},
+ {0x010143,0x0},
+ {0x110143,0x0},
+ {0x210143,0x0},
+ {0x011043,0x0},
+ {0x111043,0x0},
+ {0x211043,0x0},
+ {0x011143,0x0},
+ {0x111143,0x0},
+ {0x211143,0x0},
+ {0x000080,0x0},
+ {0x100080,0x0},
+ {0x200080,0x0},
+ {0x001080,0x0},
+ {0x101080,0x0},
+ {0x201080,0x0},
+ {0x002080,0x0},
+ {0x102080,0x0},
+ {0x202080,0x0},
+ {0x003080,0x0},
+ {0x103080,0x0},
+ {0x203080,0x0},
+ {0x004080,0x0},
+ {0x104080,0x0},
+ {0x204080,0x0},
+ {0x005080,0x0},
+ {0x105080,0x0},
+ {0x205080,0x0},
+ {0x006080,0x0},
+ {0x106080,0x0},
+ {0x206080,0x0},
+ {0x007080,0x0},
+ {0x107080,0x0},
+ {0x207080,0x0},
+ {0x008080,0x0},
+ {0x108080,0x0},
+ {0x208080,0x0},
+ {0x009080,0x0},
+ {0x109080,0x0},
+ {0x209080,0x0},
+ {0x010080,0x0},
+ {0x110080,0x0},
+ {0x210080,0x0},
+ {0x010180,0x0},
+ {0x110180,0x0},
+ {0x210180,0x0},
+ {0x010081,0x0},
+ {0x110081,0x0},
+ {0x210081,0x0},
+ {0x010181,0x0},
+ {0x110181,0x0},
+ {0x210181,0x0},
+ {0x010082,0x0},
+ {0x110082,0x0},
+ {0x210082,0x0},
+ {0x010182,0x0},
+ {0x110182,0x0},
+ {0x210182,0x0},
+ {0x010083,0x0},
+ {0x110083,0x0},
+ {0x210083,0x0},
+ {0x010183,0x0},
+ {0x110183,0x0},
+ {0x210183,0x0},
+ {0x011080,0x0},
+ {0x111080,0x0},
+ {0x211080,0x0},
+ {0x011180,0x0},
+ {0x111180,0x0},
+ {0x211180,0x0},
+ {0x011081,0x0},
+ {0x111081,0x0},
+ {0x211081,0x0},
+ {0x011181,0x0},
+ {0x111181,0x0},
+ {0x211181,0x0},
+ {0x011082,0x0},
+ {0x111082,0x0},
+ {0x211082,0x0},
+ {0x011182,0x0},
+ {0x111182,0x0},
+ {0x211182,0x0},
+ {0x011083,0x0},
+ {0x111083,0x0},
+ {0x211083,0x0},
+ {0x011183,0x0},
+ {0x111183,0x0},
+ {0x211183,0x0},
+ {0x0100d0,0x0},
+ {0x1100d0,0x0},
+ {0x2100d0,0x0},
+ {0x0101d0,0x0},
+ {0x1101d0,0x0},
+ {0x2101d0,0x0},
+ {0x0100d1,0x0},
+ {0x1100d1,0x0},
+ {0x2100d1,0x0},
+ {0x0101d1,0x0},
+ {0x1101d1,0x0},
+ {0x2101d1,0x0},
+ {0x0100d2,0x0},
+ {0x1100d2,0x0},
+ {0x2100d2,0x0},
+ {0x0101d2,0x0},
+ {0x1101d2,0x0},
+ {0x2101d2,0x0},
+ {0x0100d3,0x0},
+ {0x1100d3,0x0},
+ {0x2100d3,0x0},
+ {0x0101d3,0x0},
+ {0x1101d3,0x0},
+ {0x2101d3,0x0},
+ {0x0110d0,0x0},
+ {0x1110d0,0x0},
+ {0x2110d0,0x0},
+ {0x0111d0,0x0},
+ {0x1111d0,0x0},
+ {0x2111d0,0x0},
+ {0x0110d1,0x0},
+ {0x1110d1,0x0},
+ {0x2110d1,0x0},
+ {0x0111d1,0x0},
+ {0x1111d1,0x0},
+ {0x2111d1,0x0},
+ {0x0110d2,0x0},
+ {0x1110d2,0x0},
+ {0x2110d2,0x0},
+ {0x0111d2,0x0},
+ {0x1111d2,0x0},
+ {0x2111d2,0x0},
+ {0x0110d3,0x0},
+ {0x1110d3,0x0},
+ {0x2110d3,0x0},
+ {0x0111d3,0x0},
+ {0x1111d3,0x0},
+ {0x2111d3,0x0},
+ {0x010068,0x0},
+ {0x010168,0x0},
+ {0x010268,0x0},
+ {0x010368,0x0},
+ {0x010468,0x0},
+ {0x010568,0x0},
+ {0x010668,0x0},
+ {0x010768,0x0},
+ {0x010868,0x0},
+ {0x010069,0x0},
+ {0x010169,0x0},
+ {0x010269,0x0},
+ {0x010369,0x0},
+ {0x010469,0x0},
+ {0x010569,0x0},
+ {0x010669,0x0},
+ {0x010769,0x0},
+ {0x010869,0x0},
+ {0x01006a,0x0},
+ {0x01016a,0x0},
+ {0x01026a,0x0},
+ {0x01036a,0x0},
+ {0x01046a,0x0},
+ {0x01056a,0x0},
+ {0x01066a,0x0},
+ {0x01076a,0x0},
+ {0x01086a,0x0},
+ {0x01006b,0x0},
+ {0x01016b,0x0},
+ {0x01026b,0x0},
+ {0x01036b,0x0},
+ {0x01046b,0x0},
+ {0x01056b,0x0},
+ {0x01066b,0x0},
+ {0x01076b,0x0},
+ {0x01086b,0x0},
+ {0x011068,0x0},
+ {0x011168,0x0},
+ {0x011268,0x0},
+ {0x011368,0x0},
+ {0x011468,0x0},
+ {0x011568,0x0},
+ {0x011668,0x0},
+ {0x011768,0x0},
+ {0x011868,0x0},
+ {0x011069,0x0},
+ {0x011169,0x0},
+ {0x011269,0x0},
+ {0x011369,0x0},
+ {0x011469,0x0},
+ {0x011569,0x0},
+ {0x011669,0x0},
+ {0x011769,0x0},
+ {0x011869,0x0},
+ {0x01106a,0x0},
+ {0x01116a,0x0},
+ {0x01126a,0x0},
+ {0x01136a,0x0},
+ {0x01146a,0x0},
+ {0x01156a,0x0},
+ {0x01166a,0x0},
+ {0x01176a,0x0},
+ {0x01186a,0x0},
+ {0x01106b,0x0},
+ {0x01116b,0x0},
+ {0x01126b,0x0},
+ {0x01136b,0x0},
+ {0x01146b,0x0},
+ {0x01156b,0x0},
+ {0x01166b,0x0},
+ {0x01176b,0x0},
+ {0x01186b,0x0},
+ {0x01008c,0x0},
+ {0x11008c,0x0},
+ {0x21008c,0x0},
+ {0x01018c,0x0},
+ {0x11018c,0x0},
+ {0x21018c,0x0},
+ {0x01008d,0x0},
+ {0x11008d,0x0},
+ {0x21008d,0x0},
+ {0x01018d,0x0},
+ {0x11018d,0x0},
+ {0x21018d,0x0},
+ {0x01008e,0x0},
+ {0x11008e,0x0},
+ {0x21008e,0x0},
+ {0x01018e,0x0},
+ {0x11018e,0x0},
+ {0x21018e,0x0},
+ {0x01008f,0x0},
+ {0x11008f,0x0},
+ {0x21008f,0x0},
+ {0x01018f,0x0},
+ {0x11018f,0x0},
+ {0x21018f,0x0},
+ {0x01108c,0x0},
+ {0x11108c,0x0},
+ {0x21108c,0x0},
+ {0x01118c,0x0},
+ {0x11118c,0x0},
+ {0x21118c,0x0},
+ {0x01108d,0x0},
+ {0x11108d,0x0},
+ {0x21108d,0x0},
+ {0x01118d,0x0},
+ {0x11118d,0x0},
+ {0x21118d,0x0},
+ {0x01108e,0x0},
+ {0x11108e,0x0},
+ {0x21108e,0x0},
+ {0x01118e,0x0},
+ {0x11118e,0x0},
+ {0x21118e,0x0},
+ {0x01108f,0x0},
+ {0x11108f,0x0},
+ {0x21108f,0x0},
+ {0x01118f,0x0},
+ {0x11118f,0x0},
+ {0x21118f,0x0},
+ {0x0100c0,0x0},
+ {0x1100c0,0x0},
+ {0x2100c0,0x0},
+ {0x0101c0,0x0},
+ {0x1101c0,0x0},
+ {0x2101c0,0x0},
+ {0x0102c0,0x0},
+ {0x1102c0,0x0},
+ {0x2102c0,0x0},
+ {0x0103c0,0x0},
+ {0x1103c0,0x0},
+ {0x2103c0,0x0},
+ {0x0104c0,0x0},
+ {0x1104c0,0x0},
+ {0x2104c0,0x0},
+ {0x0105c0,0x0},
+ {0x1105c0,0x0},
+ {0x2105c0,0x0},
+ {0x0106c0,0x0},
+ {0x1106c0,0x0},
+ {0x2106c0,0x0},
+ {0x0107c0,0x0},
+ {0x1107c0,0x0},
+ {0x2107c0,0x0},
+ {0x0108c0,0x0},
+ {0x1108c0,0x0},
+ {0x2108c0,0x0},
+ {0x0100c1,0x0},
+ {0x1100c1,0x0},
+ {0x2100c1,0x0},
+ {0x0101c1,0x0},
+ {0x1101c1,0x0},
+ {0x2101c1,0x0},
+ {0x0102c1,0x0},
+ {0x1102c1,0x0},
+ {0x2102c1,0x0},
+ {0x0103c1,0x0},
+ {0x1103c1,0x0},
+ {0x2103c1,0x0},
+ {0x0104c1,0x0},
+ {0x1104c1,0x0},
+ {0x2104c1,0x0},
+ {0x0105c1,0x0},
+ {0x1105c1,0x0},
+ {0x2105c1,0x0},
+ {0x0106c1,0x0},
+ {0x1106c1,0x0},
+ {0x2106c1,0x0},
+ {0x0107c1,0x0},
+ {0x1107c1,0x0},
+ {0x2107c1,0x0},
+ {0x0108c1,0x0},
+ {0x1108c1,0x0},
+ {0x2108c1,0x0},
+ {0x0100c2,0x0},
+ {0x1100c2,0x0},
+ {0x2100c2,0x0},
+ {0x0101c2,0x0},
+ {0x1101c2,0x0},
+ {0x2101c2,0x0},
+ {0x0102c2,0x0},
+ {0x1102c2,0x0},
+ {0x2102c2,0x0},
+ {0x0103c2,0x0},
+ {0x1103c2,0x0},
+ {0x2103c2,0x0},
+ {0x0104c2,0x0},
+ {0x1104c2,0x0},
+ {0x2104c2,0x0},
+ {0x0105c2,0x0},
+ {0x1105c2,0x0},
+ {0x2105c2,0x0},
+ {0x0106c2,0x0},
+ {0x1106c2,0x0},
+ {0x2106c2,0x0},
+ {0x0107c2,0x0},
+ {0x1107c2,0x0},
+ {0x2107c2,0x0},
+ {0x0108c2,0x0},
+ {0x1108c2,0x0},
+ {0x2108c2,0x0},
+ {0x0100c3,0x0},
+ {0x1100c3,0x0},
+ {0x2100c3,0x0},
+ {0x0101c3,0x0},
+ {0x1101c3,0x0},
+ {0x2101c3,0x0},
+ {0x0102c3,0x0},
+ {0x1102c3,0x0},
+ {0x2102c3,0x0},
+ {0x0103c3,0x0},
+ {0x1103c3,0x0},
+ {0x2103c3,0x0},
+ {0x0104c3,0x0},
+ {0x1104c3,0x0},
+ {0x2104c3,0x0},
+ {0x0105c3,0x0},
+ {0x1105c3,0x0},
+ {0x2105c3,0x0},
+ {0x0106c3,0x0},
+ {0x1106c3,0x0},
+ {0x2106c3,0x0},
+ {0x0107c3,0x0},
+ {0x1107c3,0x0},
+ {0x2107c3,0x0},
+ {0x0108c3,0x0},
+ {0x1108c3,0x0},
+ {0x2108c3,0x0},
+ {0x0110c0,0x0},
+ {0x1110c0,0x0},
+ {0x2110c0,0x0},
+ {0x0111c0,0x0},
+ {0x1111c0,0x0},
+ {0x2111c0,0x0},
+ {0x0112c0,0x0},
+ {0x1112c0,0x0},
+ {0x2112c0,0x0},
+ {0x0113c0,0x0},
+ {0x1113c0,0x0},
+ {0x2113c0,0x0},
+ {0x0114c0,0x0},
+ {0x1114c0,0x0},
+ {0x2114c0,0x0},
+ {0x0115c0,0x0},
+ {0x1115c0,0x0},
+ {0x2115c0,0x0},
+ {0x0116c0,0x0},
+ {0x1116c0,0x0},
+ {0x2116c0,0x0},
+ {0x0117c0,0x0},
+ {0x1117c0,0x0},
+ {0x2117c0,0x0},
+ {0x0118c0,0x0},
+ {0x1118c0,0x0},
+ {0x2118c0,0x0},
+ {0x0110c1,0x0},
+ {0x1110c1,0x0},
+ {0x2110c1,0x0},
+ {0x0111c1,0x0},
+ {0x1111c1,0x0},
+ {0x2111c1,0x0},
+ {0x0112c1,0x0},
+ {0x1112c1,0x0},
+ {0x2112c1,0x0},
+ {0x0113c1,0x0},
+ {0x1113c1,0x0},
+ {0x2113c1,0x0},
+ {0x0114c1,0x0},
+ {0x1114c1,0x0},
+ {0x2114c1,0x0},
+ {0x0115c1,0x0},
+ {0x1115c1,0x0},
+ {0x2115c1,0x0},
+ {0x0116c1,0x0},
+ {0x1116c1,0x0},
+ {0x2116c1,0x0},
+ {0x0117c1,0x0},
+ {0x1117c1,0x0},
+ {0x2117c1,0x0},
+ {0x0118c1,0x0},
+ {0x1118c1,0x0},
+ {0x2118c1,0x0},
+ {0x0110c2,0x0},
+ {0x1110c2,0x0},
+ {0x2110c2,0x0},
+ {0x0111c2,0x0},
+ {0x1111c2,0x0},
+ {0x2111c2,0x0},
+ {0x0112c2,0x0},
+ {0x1112c2,0x0},
+ {0x2112c2,0x0},
+ {0x0113c2,0x0},
+ {0x1113c2,0x0},
+ {0x2113c2,0x0},
+ {0x0114c2,0x0},
+ {0x1114c2,0x0},
+ {0x2114c2,0x0},
+ {0x0115c2,0x0},
+ {0x1115c2,0x0},
+ {0x2115c2,0x0},
+ {0x0116c2,0x0},
+ {0x1116c2,0x0},
+ {0x2116c2,0x0},
+ {0x0117c2,0x0},
+ {0x1117c2,0x0},
+ {0x2117c2,0x0},
+ {0x0118c2,0x0},
+ {0x1118c2,0x0},
+ {0x2118c2,0x0},
+ {0x0110c3,0x0},
+ {0x1110c3,0x0},
+ {0x2110c3,0x0},
+ {0x0111c3,0x0},
+ {0x1111c3,0x0},
+ {0x2111c3,0x0},
+ {0x0112c3,0x0},
+ {0x1112c3,0x0},
+ {0x2112c3,0x0},
+ {0x0113c3,0x0},
+ {0x1113c3,0x0},
+ {0x2113c3,0x0},
+ {0x0114c3,0x0},
+ {0x1114c3,0x0},
+ {0x2114c3,0x0},
+ {0x0115c3,0x0},
+ {0x1115c3,0x0},
+ {0x2115c3,0x0},
+ {0x0116c3,0x0},
+ {0x1116c3,0x0},
+ {0x2116c3,0x0},
+ {0x0117c3,0x0},
+ {0x1117c3,0x0},
+ {0x2117c3,0x0},
+ {0x0118c3,0x0},
+ {0x1118c3,0x0},
+ {0x2118c3,0x0},
+ {0x010020,0x0},
+ {0x110020,0x0},
+ {0x210020,0x0},
+ {0x011020,0x0},
+ {0x111020,0x0},
+ {0x211020,0x0},
+ {0x02007d,0x0},
+ {0x12007d,0x0},
+ {0x22007d,0x0},
+ {0x010040,0x0},
+ {0x010140,0x0},
+ {0x010240,0x0},
+ {0x010340,0x0},
+ {0x010440,0x0},
+ {0x010540,0x0},
+ {0x010640,0x0},
+ {0x010740,0x0},
+ {0x010840,0x0},
+ {0x010030,0x0},
+ {0x010130,0x0},
+ {0x010230,0x0},
+ {0x010330,0x0},
+ {0x010430,0x0},
+ {0x010530,0x0},
+ {0x010630,0x0},
+ {0x010730,0x0},
+ {0x010830,0x0},
+ {0x011040,0x0},
+ {0x011140,0x0},
+ {0x011240,0x0},
+ {0x011340,0x0},
+ {0x011440,0x0},
+ {0x011540,0x0},
+ {0x011640,0x0},
+ {0x011740,0x0},
+ {0x011840,0x0},
+ {0x011030,0x0},
+ {0x011130,0x0},
+ {0x011230,0x0},
+ {0x011330,0x0},
+ {0x011430,0x0},
+ {0x011530,0x0},
+ {0x011630,0x0},
+ {0x011730,0x0},
+ {0x011830,0x0},
+
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0x000d0000,0x00000000},
+ {0x00020060,0x00000002},
+ {0x00054000,0x00000000},
+ {0x00054001,0x00000000},
+ {0x00054002,0x00000000},
+ {0x00054003,0x00000960},
+ {0x00054004,0x00000002},
+ {0x00054005,0x00000000},
+ {0x00054006,0x0000025e},
+ {0x00054007,0x00001000},
+ {0x00054008,0x00000101},
+ {0x00054009,0x00000000},
+ {0x0005400a,0x00000000},
+ {0x0005400b,0x0000031f},
+ {0x0005400c,0x000000c8},
+ {0x0005400d,0x00000100},
+ {0x0005400e,0x00000000},
+ {0x0005400f,0x00000000},
+ {0x00054010,0x00000000},
+ {0x00054011,0x00000000},
+ {0x00054012,0x00000001},
+ {0x0005402f,0x00000834},
+ {0x00054030,0x00000105},
+ {0x00054031,0x00000018},
+ {0x00054032,0x00000200},
+ {0x00054033,0x00000200},
+ {0x00054034,0x00000740},
+ {0x00054035,0x00000850},
+ {0x00054036,0x00000103},
+ {0x00054037,0x00000000},
+ {0x00054038,0x00000000},
+ {0x00054039,0x00000000},
+ {0x0005403a,0x00000000},
+ {0x0005403b,0x00000000},
+ {0x0005403c,0x00000000},
+ {0x0005403d,0x00000000},
+ {0x0005403e,0x00000000},
+ {0x0005403f,0x00001221},
+ {0x000541fc,0x00000100},
+ {0x000d0000,0x00000001},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0x000d0000,0x00000000},
+ {0x00054000,0x00000000},
+ {0x00054001,0x00000000},
+ {0x00054002,0x00000101},
+ {0x00054003,0x00000190},
+ {0x00054004,0x00000002},
+ {0x00054005,0x00000000},
+ {0x00054006,0x0000025e},
+ {0x00054007,0x00001000},
+ {0x00054008,0x00000101},
+ {0x00054009,0x00000000},
+ {0x0005400a,0x00000000},
+ {0x0005400b,0x0000021f},
+ {0x0005400c,0x000000c8},
+ {0x0005400d,0x00000100},
+ {0x0005400e,0x00000000},
+ {0x0005400f,0x00000000},
+ {0x00054010,0x00000000},
+ {0x00054011,0x00000000},
+ {0x00054012,0x00000001},
+ {0x0005402f,0x00000000},
+ {0x00054030,0x00000105},
+ {0x00054031,0x00000000},
+ {0x00054032,0x00000000},
+ {0x00054033,0x00000200},
+ {0x00054034,0x00000740},
+ {0x00054035,0x00000050},
+ {0x00054036,0x00000103},
+ {0x00054037,0x00000000},
+ {0x00054038,0x00000000},
+ {0x00054039,0x00000000},
+ {0x0005403a,0x00000000},
+ {0x0005403b,0x00000000},
+ {0x0005403c,0x00000000},
+ {0x0005403d,0x00000000},
+ {0x0005403e,0x00000000},
+ {0x0005403f,0x00001221},
+ {0x000541fc,0x00000100},
+ {0x000d0000,0x00000001},
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0x000d0000,0x00000000},
+ {0x00054000,0x00000000},
+ {0x00054001,0x00000000},
+ {0x00054002,0x00000102},
+ {0x00054003,0x00000064},
+ {0x00054004,0x00000002},
+ {0x00054005,0x00000000},
+ {0x00054006,0x0000025e},
+ {0x00054007,0x00001000},
+ {0x00054008,0x00000101},
+ {0x00054009,0x00000000},
+ {0x0005400a,0x00000000},
+ {0x0005400b,0x0000021f},
+ {0x0005400c,0x000000c8},
+ {0x0005400d,0x00000100},
+ {0x0005400e,0x00000000},
+ {0x0005400f,0x00000000},
+ {0x00054010,0x00000000},
+ {0x00054011,0x00000000},
+ {0x00054012,0x00000001},
+ {0x0005402f,0x00000000},
+ {0x00054030,0x00000105},
+ {0x00054031,0x00000000},
+ {0x00054032,0x00000000},
+ {0x00054033,0x00000200},
+ {0x00054034,0x00000740},
+ {0x00054035,0x00000050},
+ {0x00054036,0x00000103},
+ {0x00054037,0x00000000},
+ {0x00054038,0x00000000},
+ {0x00054039,0x00000000},
+ {0x0005403a,0x00000000},
+ {0x0005403b,0x00000000},
+ {0x0005403c,0x00000000},
+ {0x0005403d,0x00000000},
+ {0x0005403e,0x00000000},
+ {0x0005403f,0x00001221},
+ {0x000541fc,0x00000100},
+ {0x000d0000,0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0x000d0000,0x00000000},
+ {0x00054000,0x00000000},
+ {0x00054001,0x00000000},
+ {0x00054002,0x00000000},
+ {0x00054003,0x00000960},
+ {0x00054004,0x00000002},
+ {0x00054005,0x00000000},
+ {0x00054006,0x0000025e},
+ {0x00054007,0x00001000},
+ {0x00054008,0x00000101},
+ {0x00054009,0x00000000},
+ {0x0005400a,0x00000000},
+ {0x0005400b,0x00000061},
+ {0x0005400c,0x000000c8},
+ {0x0005400d,0x00000100},
+ {0x0005400e,0x00001f7f},
+ {0x0005400f,0x00000000},
+ {0x00054010,0x00000000},
+ {0x00054011,0x00000000},
+ {0x00054012,0x00000001},
+ {0x0005402f,0x00000834},
+ {0x00054030,0x00000105},
+ {0x00054031,0x00000018},
+ {0x00054032,0x00000200},
+ {0x00054033,0x00000200},
+ {0x00054034,0x00000740},
+ {0x00054035,0x00000850},
+ {0x00054036,0x00000103},
+ {0x00054037,0x00000000},
+ {0x00054038,0x00000000},
+ {0x00054039,0x00000000},
+ {0x0005403a,0x00000000},
+ {0x0005403b,0x00000000},
+ {0x0005403c,0x00000000},
+ {0x0005403d,0x00000000},
+ {0x0005403e,0x00000000},
+ {0x0005403f,0x00001221},
+ {0x000541fc,0x00000100},
+ {0x000d0000,0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000,0x0},
+ {0x90000,0x10},
+ {0x90001,0x400},
+ {0x90002,0x10e},
+ {0x90003,0x0},
+ {0x90004,0x0},
+ {0x90005,0x8},
+ {0x90029,0xb},
+ {0x9002a,0x480},
+ {0x9002b,0x109},
+ {0x9002c,0x8},
+ {0x9002d,0x448},
+ {0x9002e,0x139},
+ {0x9002f,0x8},
+ {0x90030,0x478},
+ {0x90031,0x109},
+ {0x90032,0x2},
+ {0x90033,0x10},
+ {0x90034,0x139},
+ {0x90035,0xb},
+ {0x90036,0x7c0},
+ {0x90037,0x139},
+ {0x90038,0x44},
+ {0x90039,0x633},
+ {0x9003a,0x159},
+ {0x9003b,0x14f},
+ {0x9003c,0x630},
+ {0x9003d,0x159},
+ {0x9003e,0x47},
+ {0x9003f,0x633},
+ {0x90040,0x149},
+ {0x90041,0x4f},
+ {0x90042,0x633},
+ {0x90043,0x179},
+ {0x90044,0x8},
+ {0x90045,0xe0},
+ {0x90046,0x109},
+ {0x90047,0x0},
+ {0x90048,0x7c8},
+ {0x90049,0x109},
+ {0x9004a,0x0},
+ {0x9004b,0x1},
+ {0x9004c,0x8},
+ {0x9004d,0x0},
+ {0x9004e,0x45a},
+ {0x9004f,0x9},
+ {0x90050,0x0},
+ {0x90051,0x448},
+ {0x90052,0x109},
+ {0x90053,0x40},
+ {0x90054,0x633},
+ {0x90055,0x179},
+ {0x90056,0x1},
+ {0x90057,0x618},
+ {0x90058,0x109},
+ {0x90059,0x40c0},
+ {0x9005a,0x633},
+ {0x9005b,0x149},
+ {0x9005c,0x8},
+ {0x9005d,0x4},
+ {0x9005e,0x48},
+ {0x9005f,0x4040},
+ {0x90060,0x633},
+ {0x90061,0x149},
+ {0x90062,0x0},
+ {0x90063,0x4},
+ {0x90064,0x48},
+ {0x90065,0x40},
+ {0x90066,0x633},
+ {0x90067,0x149},
+ {0x90068,0x10},
+ {0x90069,0x4},
+ {0x9006a,0x18},
+ {0x9006b,0x0},
+ {0x9006c,0x4},
+ {0x9006d,0x78},
+ {0x9006e,0x549},
+ {0x9006f,0x633},
+ {0x90070,0x159},
+ {0x90071,0xd49},
+ {0x90072,0x633},
+ {0x90073,0x159},
+ {0x90074,0x94a},
+ {0x90075,0x633},
+ {0x90076,0x159},
+ {0x90077,0x441},
+ {0x90078,0x633},
+ {0x90079,0x149},
+ {0x9007a,0x42},
+ {0x9007b,0x633},
+ {0x9007c,0x149},
+ {0x9007d,0x1},
+ {0x9007e,0x633},
+ {0x9007f,0x149},
+ {0x90080,0x0},
+ {0x90081,0xe0},
+ {0x90082,0x109},
+ {0x90083,0xa},
+ {0x90084,0x10},
+ {0x90085,0x109},
+ {0x90086,0x9},
+ {0x90087,0x3c0},
+ {0x90088,0x149},
+ {0x90089,0x9},
+ {0x9008a,0x3c0},
+ {0x9008b,0x159},
+ {0x9008c,0x18},
+ {0x9008d,0x10},
+ {0x9008e,0x109},
+ {0x9008f,0x0},
+ {0x90090,0x3c0},
+ {0x90091,0x109},
+ {0x90092,0x18},
+ {0x90093,0x4},
+ {0x90094,0x48},
+ {0x90095,0x18},
+ {0x90096,0x4},
+ {0x90097,0x58},
+ {0x90098,0xb},
+ {0x90099,0x10},
+ {0x9009a,0x109},
+ {0x9009b,0x1},
+ {0x9009c,0x10},
+ {0x9009d,0x109},
+ {0x9009e,0x5},
+ {0x9009f,0x7c0},
+ {0x900a0,0x109},
+ {0x900a1,0x0},
+ {0x900a2,0x8140},
+ {0x900a3,0x10c},
+ {0x900a4,0x10},
+ {0x900a5,0x8138},
+ {0x900a6,0x10c},
+ {0x900a7,0x8},
+ {0x900a8,0x7c8},
+ {0x900a9,0x101},
+ {0x900aa,0x8},
+ {0x900ab,0x448},
+ {0x900ac,0x109},
+ {0x900ad,0xf},
+ {0x900ae,0x7c0},
+ {0x900af,0x109},
+ {0x900b0,0x47},
+ {0x900b1,0x630},
+ {0x900b2,0x109},
+ {0x900b3,0x8},
+ {0x900b4,0x618},
+ {0x900b5,0x109},
+ {0x900b6,0x8},
+ {0x900b7,0xe0},
+ {0x900b8,0x109},
+ {0x900b9,0x0},
+ {0x900ba,0x7c8},
+ {0x900bb,0x109},
+ {0x900bc,0x8},
+ {0x900bd,0x8140},
+ {0x900be,0x10c},
+ {0x900bf,0x0},
+ {0x900c0,0x1},
+ {0x900c1,0x8},
+ {0x900c2,0x8},
+ {0x900c3,0x4},
+ {0x900c4,0x8},
+ {0x900c5,0x8},
+ {0x900c6,0x7c8},
+ {0x900c7,0x101},
+ {0x90006,0x0},
+ {0x90007,0x0},
+ {0x90008,0x8},
+ {0x90009,0x0},
+ {0x9000a,0x0},
+ {0x9000b,0x0},
+ {0xd00e7,0x400},
+ {0x90017,0x0},
+ {0x90026,0x2b},
+ {0x2000b,0x4b},
+ {0x2000c,0x96},
+ {0x2000d,0x5dc},
+ {0x2000e,0x2c},
+ {0x12000b,0xc},
+ {0x12000c,0x16},
+ {0x12000d,0xfa},
+ {0x12000e,0x10},
+ {0x22000b,0x3},
+ {0x22000c,0x3},
+ {0x22000d,0x3e},
+ {0x22000e,0x10},
+ {0x9000c,0x0},
+ {0x9000d,0x173},
+ {0x9000e,0x60},
+ {0x9000f,0x6110},
+ {0x90010,0x2152},
+ {0x90011,0xdfbd},
+ {0x90012,0xffff},
+ {0x90013,0x6152},
+ {0x20089,0x1},
+ {0x20088,0x19},
+ {0xc0080,0x0},
+ {0xd0000,0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 400, 100,},
+};
+
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <asm/mach-imx/dma.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include "../common/tcpc.h"
+#include <usb.h>
+#include <sec_mipi_dsim.h>
+#include <imx_mipi_dsi_bridge.h>
+#include <mipi_dsi_panel.h>
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_FSPI
+int board_qspi_init(void)
+{
+ set_clk_qspi();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+static iomux_v3_cfg_t const gpmi_pads[] = {
+ IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+ IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+ init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(1);
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MN_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(FEC_RST_PAD, "fec1_rst");
+ gpio_direction_output(FEC_RST_PAD, 0);
+ udelay(500);
+ gpio_direction_output(FEC_RST_PAD, 1);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+ struct udevice *bus;
+ struct udevice *i2c_dev = NULL;
+ int ret;
+ uint8_t valb;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+ if (ret) {
+ printf("%s: Can't find bus\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+ if (ret) {
+ printf("%s: Can't find device id=0x%x\n",
+ __func__, addr);
+ return -ENODEV;
+ }
+
+ ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+ if (ret) {
+ printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+ return -EIO;
+ }
+ valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+ ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+ if (ret) {
+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+ return -EIO;
+ }
+
+ /* Set OVP threshold to 23V */
+ valb = 0x6;
+ ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+ if (ret) {
+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+ if (port == &port1) {
+ debug("Setup pd switch on port 1\n");
+ return setup_pd_switch(1, 0x72);
+ } else if (port == &port2) {
+ debug("Setup pd switch on port 2\n");
+ return setup_pd_switch(1, 0x73);
+ } else
+ return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+ .i2c_bus = 1, /*i2c2*/
+ .addr = 0x50,
+ .port_type = TYPEC_PORT_UFP,
+ .max_snk_mv = 5000,
+ .max_snk_ma = 3000,
+ .max_snk_mw = 40000,
+ .op_snk_mv = 9000,
+ .switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+ .i2c_bus = 1, /*i2c2*/
+ .addr = 0x52,
+ .port_type = TYPEC_PORT_UFP,
+ .max_snk_mv = 5000,
+ .max_snk_ma = 3000,
+ .max_snk_mw = 40000,
+ .op_snk_mv = 9000,
+ .switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+ int ret;
+
+ debug("tcpc_init port 2\n");
+ ret = tcpc_init(&port2, port2_config, NULL);
+ if (ret) {
+ printf("%s: tcpc port2 init failed, err=%d\n",
+ __func__, ret);
+ } else if (tcpc_pd_sink_check_charging(&port2)) {
+ /* Disable PD for USB1, since USB2 has priority */
+ port1_config.disable_pd = true;
+ printf("Power supply on USB2\n");
+ }
+
+ debug("tcpc_init port 1\n");
+ ret = tcpc_init(&port1, port1_config, NULL);
+ if (ret) {
+ printf("%s: tcpc port1 init failed, err=%d\n",
+ __func__, ret);
+ } else {
+ if (!port1_config.disable_pd)
+ printf("Power supply on USB1\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ struct tcpc_port *port_ptr;
+
+ debug("board_usb_init %d, type %d\n", index, init);
+
+ if (index == 0)
+ port_ptr = &port1;
+ else
+ port_ptr = &port2;
+
+ imx8m_usb_power(index, true);
+
+ if (init == USB_INIT_HOST)
+ tcpc_setup_dfp_mode(port_ptr);
+ else
+ tcpc_setup_ufp_mode(port_ptr);
+
+ return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ debug("board_usb_cleanup %d, type %d\n", index, init);
+
+ if (init == USB_INIT_HOST) {
+ if (index == 0)
+ ret = tcpc_disable_src_vbus(&port1);
+ else
+ ret = tcpc_disable_src_vbus(&port2);
+ }
+
+ imx8m_usb_power(index, false);
+ return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+ int ret = 0;
+ enum typec_cc_polarity pol;
+ enum typec_cc_state state;
+ struct tcpc_port *port_ptr;
+
+ if (dev->seq == 0)
+ port_ptr = &port1;
+ else
+ port_ptr = &port2;
+
+ tcpc_setup_ufp_mode(port_ptr);
+
+ ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+ if (!ret) {
+ if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+ return USB_INIT_HOST;
+ }
+
+ return USB_INIT_DEVICE;
+}
+
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_USB_TCPC
+ setup_typec();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#ifdef CONFIG_FSL_FSPI
+ board_qspi_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_VIDEO_MXS
+
+#define ADV7535_MAIN 0x3d
+#define ADV7535_DSI_CEC 0x3c
+
+static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
+ .version = 0x1060200,
+ .max_data_lanes = 4,
+ .max_data_rate = 1500000000ULL,
+ .reg_base = MIPI_DSI_BASE_ADDR,
+ .gpr_base = CSI_BASE_ADDR + 0x8000,
+};
+
+static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
+{
+ uint8_t valb;
+ int err;
+
+ if (mask != 0xff) {
+ err = dm_i2c_read(dev, addr, &valb, 1);
+ if (err)
+ return err;
+
+ valb &= ~mask;
+ valb |= data;
+ } else {
+ valb = data;
+ }
+
+ err = dm_i2c_write(dev, addr, &valb, 1);
+ return err;
+}
+
+static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data)
+{
+ uint8_t valb;
+ int err;
+
+ err = dm_i2c_read(dev, addr, &valb, 1);
+ if (err)
+ return err;
+
+ *data = (int)valb;
+ return 0;
+}
+
+static void adv7535_init(void)
+{
+ struct udevice *bus, *main_dev, *cec_dev;
+ int i2c_bus = 1;
+ int ret;
+ uint8_t val;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+ if (ret) {
+ printf("%s: No bus %d\n", __func__, i2c_bus);
+ return;
+ }
+
+ ret = dm_i2c_probe(bus, ADV7535_MAIN, 0, &main_dev);
+ if (ret) {
+ printf("%s: Can't find device id=0x%x, on bus %d\n",
+ __func__, ADV7535_MAIN, i2c_bus);
+ return;
+ }
+
+ ret = dm_i2c_probe(bus, ADV7535_DSI_CEC, 0, &cec_dev);
+ if (ret) {
+ printf("%s: Can't find device id=0x%x, on bus %d\n",
+ __func__, ADV7535_MAIN, i2c_bus);
+ return;
+ }
+
+ adv7535_i2c_reg_read(main_dev, 0x00, &val);
+ debug("Chip revision: 0x%x (expected: 0x14)\n", val);
+ adv7535_i2c_reg_read(cec_dev, 0x00, &val);
+ debug("Chip ID MSB: 0x%x (expected: 0x75)\n", val);
+ adv7535_i2c_reg_read(cec_dev, 0x01, &val);
+ debug("Chip ID LSB: 0x%x (expected: 0x33)\n", val);
+
+ /* Power */
+ adv7535_i2c_reg_write(main_dev, 0x41, 0xff, 0x10);
+ /* Initialisation (Fixed) Registers */
+ adv7535_i2c_reg_write(main_dev, 0x16, 0xff, 0x20);
+ adv7535_i2c_reg_write(main_dev, 0x9A, 0xff, 0xE0);
+ adv7535_i2c_reg_write(main_dev, 0xBA, 0xff, 0x70);
+ adv7535_i2c_reg_write(main_dev, 0xDE, 0xff, 0x82);
+ adv7535_i2c_reg_write(main_dev, 0xE4, 0xff, 0x40);
+ adv7535_i2c_reg_write(main_dev, 0xE5, 0xff, 0x80);
+ adv7535_i2c_reg_write(cec_dev, 0x15, 0xff, 0xD0);
+ adv7535_i2c_reg_write(cec_dev, 0x17, 0xff, 0xD0);
+ adv7535_i2c_reg_write(cec_dev, 0x24, 0xff, 0x20);
+ adv7535_i2c_reg_write(cec_dev, 0x57, 0xff, 0x11);
+ /* 4 x DSI Lanes */
+ adv7535_i2c_reg_write(cec_dev, 0x1C, 0xff, 0x40);
+
+ /* DSI Pixel Clock Divider */
+ adv7535_i2c_reg_write(cec_dev, 0x16, 0xff, 0x18);
+
+ /* Enable Internal Timing Generator */
+ adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
+ /* 1920 x 1080p 60Hz */
+ adv7535_i2c_reg_write(cec_dev, 0x28, 0xff, 0x89); /* total width */
+ adv7535_i2c_reg_write(cec_dev, 0x29, 0xff, 0x80); /* total width */
+ adv7535_i2c_reg_write(cec_dev, 0x2A, 0xff, 0x02); /* hsync */
+ adv7535_i2c_reg_write(cec_dev, 0x2B, 0xff, 0xC0); /* hsync */
+ adv7535_i2c_reg_write(cec_dev, 0x2C, 0xff, 0x05); /* hfp */
+ adv7535_i2c_reg_write(cec_dev, 0x2D, 0xff, 0x80); /* hfp */
+ adv7535_i2c_reg_write(cec_dev, 0x2E, 0xff, 0x09); /* hbp */
+ adv7535_i2c_reg_write(cec_dev, 0x2F, 0xff, 0x40); /* hbp */
+
+ adv7535_i2c_reg_write(cec_dev, 0x30, 0xff, 0x46); /* total height */
+ adv7535_i2c_reg_write(cec_dev, 0x31, 0xff, 0x50); /* total height */
+ adv7535_i2c_reg_write(cec_dev, 0x32, 0xff, 0x00); /* vsync */
+ adv7535_i2c_reg_write(cec_dev, 0x33, 0xff, 0x50); /* vsync */
+ adv7535_i2c_reg_write(cec_dev, 0x34, 0xff, 0x00); /* vfp */
+ adv7535_i2c_reg_write(cec_dev, 0x35, 0xff, 0x40); /* vfp */
+ adv7535_i2c_reg_write(cec_dev, 0x36, 0xff, 0x02); /* vbp */
+ adv7535_i2c_reg_write(cec_dev, 0x37, 0xff, 0x40); /* vbp */
+
+ /* Reset Internal Timing Generator */
+ adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
+ adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0x8B);
+ adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
+
+ /* HDMI Output */
+ adv7535_i2c_reg_write(main_dev, 0xAF, 0xff, 0x16);
+ /* AVI Infoframe - RGB - 16-9 Aspect Ratio */
+ adv7535_i2c_reg_write(main_dev, 0x55, 0xff, 0x02);
+ adv7535_i2c_reg_write(main_dev, 0x56, 0xff, 0x0);
+
+ /* GC Packet Enable */
+ adv7535_i2c_reg_write(main_dev, 0x40, 0xff, 0x0);
+ /* GC Colour Depth - 24 Bit */
+ adv7535_i2c_reg_write(main_dev, 0x4C, 0xff, 0x0);
+ /* Down Dither Output Colour Depth - 8 Bit (default) */
+ adv7535_i2c_reg_write(main_dev, 0x49, 0xff, 0x00);
+
+ /* set low refresh 1080p30 */
+ adv7535_i2c_reg_write(main_dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/
+
+ /* HDMI Output Enable */
+ adv7535_i2c_reg_write(cec_dev, 0xbe, 0xff, 0x3c);
+ adv7535_i2c_reg_write(cec_dev, 0x03, 0xff, 0x89);
+}
+
+#define DISPLAY_MIX_SFT_RSTN_CSR 0x00
+#define DISPLAY_MIX_CLK_EN_CSR 0x04
+
+ /* 'DISP_MIX_SFT_RSTN_CSR' bit fields */
+#define BUS_RSTN_BLK_SYNC_SFT_EN BIT(8)
+#define LCDIF_APB_CLK_RSTN BIT(5)
+#define LCDIF_PIXEL_CLK_RSTN BIT(4)
+
+ /* 'DISP_MIX_CLK_EN_CSR' bit fields */
+#define BUS_BLK_CLK_SFT_EN BIT(8)
+#define LCDIF_PIXEL_CLK_SFT_EN BIT(5)
+#define LCDIF_APB_CLK_SFT_EN BIT(4)
+
+void disp_mix_bus_rstn_reset(ulong gpr_base, bool reset)
+{
+ if (!reset)
+ /* release reset */
+ setbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN | LCDIF_APB_CLK_RSTN |LCDIF_PIXEL_CLK_RSTN);
+ else
+ /* hold reset */
+ clrbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN | LCDIF_APB_CLK_RSTN |LCDIF_PIXEL_CLK_RSTN);
+}
+
+void disp_mix_lcdif_clks_enable(ulong gpr_base, bool enable)
+{
+ if (enable)
+ /* enable lcdif clks */
+ setbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, BUS_BLK_CLK_SFT_EN | LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
+ else
+ /* disable lcdif clks */
+ clrbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, BUS_BLK_CLK_SFT_EN | LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
+}
+
+struct mipi_dsi_client_dev adv7535_dev = {
+ .channel = 0,
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+ .name = "ADV7535",
+};
+
+struct mipi_dsi_client_dev rm67191_dev = {
+ .channel = 0,
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+};
+
+#define FSL_SIP_GPC 0xC2000000
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3
+#define DISPMIX 9
+#define MIPI 10
+
+void do_enable_mipi2hdmi(struct display_info_t const *dev)
+{
+ gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+ gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
+
+ /* ADV7353 initialization */
+ adv7535_init();
+
+ /* enable the dispmix & mipi phy power domain */
+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
+
+ /* Put lcdif out of reset */
+ disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
+ disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
+
+ /* Setup mipi dsim */
+ sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
+ imx_mipi_dsi_bridge_attach(&adv7535_dev); /* attach adv7535 device */
+}
+
+void do_enable_mipi_led(struct display_info_t const *dev)
+{
+ gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+ gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
+ mdelay(100);
+ gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
+
+ /* enable the dispmix & mipi phy power domain */
+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
+
+ /* Put lcdif out of reset */
+ disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
+ disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
+
+ /* Setup mipi dsim */
+ sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
+
+ rm67191_init();
+ rm67191_dev.name = displays[1].mode.name;
+ imx_mipi_dsi_bridge_attach(&rm67191_dev); /* attach rm67191 device */
+}
+
+void board_quiesce_devices(void)
+{
+ gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+ gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = LCDIF_BASE_ADDR,
+ .addr = 0,
+ .pixfmt = 24,
+ .detect = NULL,
+ .enable = do_enable_mipi2hdmi,
+ .mode = {
+ .name = "MIPI2HDMI",
+ .refresh = 60,
+ .xres = 1920,
+ .yres = 1080,
+ .pixclock = 6734, /* 148500000 */
+ .left_margin = 148,
+ .right_margin = 88,
+ .upper_margin = 36,
+ .lower_margin = 4,
+ .hsync_len = 44,
+ .vsync_len = 5,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+
+} }, {
+ .bus = LCDIF_BASE_ADDR,
+ .addr = 0,
+ .pixfmt = 24,
+ .detect = NULL,
+ .enable = do_enable_mipi_led,
+ .mode = {
+ .name = "RM67191_OLED",
+ .refresh = 60,
+ .xres = 1080,
+ .yres = 1920,
+ .pixclock = 7575, /* 132000000 */
+ .left_margin = 34,
+ .right_margin = 20,
+ .upper_margin = 4,
+ .lower_margin = 10,
+ .hsync_len = 2,
+ .vsync_len = 2,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MN_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MN_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 15)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
+
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IMX8MN_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MN_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ IMX8MN_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR, 0, 1},
+ {USDHC3_BASE_ADDR, 0, 1},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ case 1:
+ init_clk_usdhc(2);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ ret = power_bd71837_init(I2C_PMIC);
+ if (ret)
+ printf("power init failed");
+
+ p = pmic_get("BD71837");
+ pmic_probe(p);
+
+
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
+
+ /* unlock the PMIC regs */
+ pmic_reg_write(p, BD71837_REGLOCK, 0x1);
+
+ /* increase VDD_SOC/VDD_DRAM to typical value 0.95v for 3Ghz DDRs */
+ pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x19);
+
+#ifdef CONFIG_IMX8M_DDR4
+ /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+ pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
+#endif
+
+ /* lock the PMIC regs */
+ pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* Adjust pmic voltage to 1.0V for 800M */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x912000"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mn-ddr4-evk"
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_OF_CONTROL=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_PMIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_VIDEO=y
+CONFIG_IMX_SEC_MIPI_DSI=y
+
+CONFIG_SPL_IMX_ROMAPI_SUPPORT=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX8MN_EVK_H
+#define __IMX8MN_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#include "imx_env.h"
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x95fff0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00950000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00940000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 /* 64 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_MALLOC_F_ADDR 0x00940000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_BD71837
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DMA_SUPPORT
+#define CONFIG_SPL_NAND_MXS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+ (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+#endif
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "emmc_dev=2\0"\
+ "sd_dev=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET (60 << 20)
+#endif
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE SZ_32M
+#define FSL_FSPI_FLASH_NUM 1
+#define FSPI0_BASE_ADDR 0x30bb0000
+#define FSPI0_AMBA_BASE 0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
+
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#ifdef CONFIG_CMD_UBI
+#define CONFIG_MTD_DEVICE
+#endif
+#endif /* CONFIG_NAND_MXS */
+
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#endif
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#endif
+
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_CI_UDC
+
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_RM67191
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+#endif
projects / u-boot.git / commitdiff