write16(state, TXDA_CYA_AUXDA_CYA_ADDR, 0x0001);
+ write16(state, TX_DIG_CTRL_REG_1_ADDR, 0x3);
write16(state, TX_DIG_CTRL_REG_2_ADDR, 0x0024);
reg_val = read16(state, TX_ANA_CTRL_REG_1_ADDR);
write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2018);
write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2098);
write16(state, TX_ANA_CTRL_REG_2_ADDR, 0x030C);
- write16(state, TX_ANA_CTRL_REG_5_ADDR, 0x0000);
+ write16(state, TX_ANA_CTRL_REG_5_ADDR, 0x0010);
write16(state, TX_ANA_CTRL_REG_4_ADDR, 0x4001);
write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2198);
write16(state, TX_ANA_CTRL_REG_2_ADDR, 0x030D);
#define XCVR_DIAG_RX_LANE_CAL_RST_TMR_ADDR 0x40EA
#define TX_ANA_CTRL_REG_1_ADDR 0x5020
#define TX_ANA_CTRL_REG_2_ADDR 0x5021
+#define TX_DIG_CTRL_REG_1_ADDR 0x5023
#define TX_DIG_CTRL_REG_2_ADDR 0x5024
#define TXDA_CYA_AUXDA_CYA_ADDR 0x5025
#define TX_ANA_CTRL_REG_3_ADDR 0x5026