MLK-17586-4 ARM: dts: improve usdhc root clock rate

Confirm with IC, HS400 MAX clock Freq for Instance 0 is 198Mhz
and for Instance 1 is 192MHz, so set the usdhc parent clock at
396MHz, due to current APLL is config to 529.2MHz, use the formula
APLL_PFD clock = APLL * 18 / i, the nearest clock is 381.024MHz when
the i is 25, so the usdhc root clock is 190.512MHz.

But eMMC HS400 can't pass stress test at 190.512MHz, will meet CRC
error sometimes, only when down to 176.4MHz can pass the stress test.

This patch make the usdhc0 and usdhc1 root clock both source from
IMX7ULP_CLK_APLL_PFD1, and set this APLL_PFD1 clcok rate at 352.8MHz,
and set the USDHC0 root clock at 352.8MHz, and set the USDHC1 root
clock at 176.4MHz.

Also remove the clk_prepare_enable() and clk_disable_unprepare() for
APLL_PFD2, bacause U-Boot already gate off APLL_PFD1, not need to do
this again.

Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index f5e900a..b22d970 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -380,6 +380,9 @@
                                 <&clks IMX7ULP_CLK_USDHC0>;
                        clock-names ="ipg", "ahb", "per";
                        bus-width = <4>;
+                       assigned-clocks = <&clks IMX7ULP_CLK_APLL_PFD1>, <&clks IMX7ULP_CLK_USDHC0>;
+                       assigned-clock-parents = <0>, <&clks IMX7ULP_CLK_APLL_PFD1>;
+                       assigned-clock-rates = <0>, <352800000>;
                        fsl,tuning-start-tap = <20>;
                        fsl,tuning-step= <2>;
                        status = "disabled";
@@ -394,6 +397,9 @@
                                 <&clks IMX7ULP_CLK_USDHC1>;
                        clock-names ="ipg", "ahb", "per";
                        bus-width = <4>;
+                       assigned-clocks = <&clks IMX7ULP_CLK_APLL_PFD1>, <&clks IMX7ULP_CLK_USDHC1>;
+                       assigned-clock-parents = <0>, <&clks IMX7ULP_CLK_APLL_PFD1>;
+                       assigned-clock-rates = <0>, <176400000>;
                        fsl,tuning-start-tap = <20>;
                        fsl,tuning-step= <2>;
                        status = "disabled";
@@ -432,10 +438,8 @@
                        clock-names = "rosc", "sosc", "sirc",
                                "firc", "upll", "mpll";
                        #clock-cells = <1>;
-                       assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
-                                         <&clks IMX7ULP_CLK_USDHC1>;
-                       assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>,
-                                                <&clks IMX7ULP_CLK_NIC1_DIV>;
+                       assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>;
+                       assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
                };
 
                pcc2: pcc2@403F0000 {

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index b2e24e3..a2853b5 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -208,11 +208,11 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node)
         imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]);
         imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]);
 
-       /* make sure PFD is gated before setting its rate */
-       clk_prepare_enable(clks[IMX7ULP_CLK_APLL_PFD2]);
-       clk_disable_unprepare(clks[IMX7ULP_CLK_APLL_PFD2]);
        imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000);
 
+       /* setting the rate for emmc/sd usage */
+       imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD1], 352800000);
+
        pr_info("i.MX7ULP clock tree init done.\n");
 }