MLK-17798: ARM64: dts: configure IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB

The ESAI and SPDIF pin are in enet bank, the board is using 3.3v,
so we need to configure the PSW_OVR to zero, whose default setting
is for 2.5V.

Signed-off-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 6ac1c02..986d258 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -173,6 +173,7 @@
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0
                        >;
                };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index 9b51a8f..b9db4ce 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -226,6 +226,7 @@
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0       0x0600004c
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0
                        >;
                };
 

diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
index e9fe2d0..93ff8a5 100644 (file)
--- a/include/dt-bindings/pinctrl/pads-imx8qxp.h
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -421,6 +421,7 @@
 #define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12                      SC_P_SPDIF0_EXT_CLK                2
 #define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M          SC_P_SPDIF0_EXT_CLK                3
 #define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12                     SC_P_SPDIF0_EXT_CLK                4
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD                 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
 #define SC_P_SPI3_SCK_ADMA_SPI3_SCK                             SC_P_SPI3_SCK                      0
 #define SC_P_SPI3_SCK_ADMA_LCDIF_D13                            SC_P_SPI3_SCK                      2
 #define SC_P_SPI3_SCK_LSIO_GPIO0_IO13                           SC_P_SPI3_SCK                      4