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ARM: zynq: DT: Add missing interrupt for L2 pl310
authorAlex Wilson <alex.david.wilson@gmail.com>
Sat, 18 Jul 2015 02:23:55 +0000 (20:23 -0600)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 31 Jul 2015 08:50:05 +0000 (10:50 +0200)
Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/boot/dts/zynq-7000.dtsi patch | blob | history

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index d373b38..ac0a6a0 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -139,6 +139,7 @@
                L2: cache-controller@f8f02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
+                       interrupts = <0 2 4>;
                        arm,data-latency = <3 2 2>;
                        arm,tag-latency = <2 2 2>;
                        cache-unified;