MLK-12203-1 ARM: imx: adjust i.MX7D DDR retention mode for LPSR

Per design team's recommendation, for i.MX7D TO1.1
LPSR mode, as IOMUXC will lost power, so it needs to
use TO1.0's flow to avoid CKE toggle during retention,
but it has a limitation of POR reset fail during LPSR.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S
index df78a92..074efdc 100644 (file)
--- a/arch/arm/mach-imx/suspend-imx7.S
+++ b/arch/arm/mach-imx/suspend-imx7.S
@@ -309,7 +309,12 @@
        ldr     r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET]
        ldr     r7, =0x38000000
        str     r7, [r11]
-       b       11f
+
+       /* LPSR mode need to use TO1.0 flow as IOMUX lost power */
+       ldr     r10, [r0, #PM_INFO_MX7_LPSR_V_OFFSET]
+       ldr     r7, [r10]
+       cmp     r7, #0x0
+       beq     11f
 10:
        /* reset ddr_phy  */
        ldr     r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET]