Set the max link capability of the imx pcie to gen2
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
+ fsl,max-link-speed = <2>;
status = "disabled";
};
};
};
-&pcie {
- status = "disabled";
-};
-
&iomuxc {
imx6qdl-sabresd {
pinctrl_usdhc2: usdhc2grp {
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
pcie-phy-supply = <®_pcie_phy>;
power-domains = <&gpc 2>;
+ fsl,max-link-speed = <2>;
status = "disabled";
};
};
<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
pcie-phy-supply = <®_1p0d>;
+ fsl,max-link-speed = <2>;
status = "disabled";
};
};