MLK-16834-03: hdmi/dp phy: Enable additional PLL loop Amplifier.
authorSandor Yu <Sandor.yu@nxp.com>
Thu, 16 Nov 2017 03:48:38 +0000 (11:48 +0800)
committerLeonard Crestez <leonard.crestez@nxp.com>
Wed, 17 Apr 2019 23:51:34 +0000 (02:51 +0300)
Addresses the PLL lock issue found on many devices.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 5e16126749b90e3e53fc8872b87d310ce808f84e)

drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.c
drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c

index 799162f..e437120 100644 (file)
@@ -320,7 +320,7 @@ void AFE_init(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
        val = val | 0x0008;
        Afe_write(state, PHY_PMA_CMN_CTRL1, val);
 
-       Afe_write(state, CMN_DIAG_PLL0_TEST_MODE, 0x0020);
+       Afe_write(state, CMN_DIAG_PLL0_TEST_MODE, 0x0022);
        Afe_write(state, CMN_PSM_CLK_CTRL, 0x0016);
 
        phy_cfg_24mhz(state, num_lanes);
index 861cc63..be58b46 100644 (file)
@@ -205,7 +205,7 @@ int phy_cfg_hdp_ss28fdsoi(state_struct *state, int num_lanes, VIC_MODES vicMode,
                        Afe_write(state, 0x40E8 | (i << 9), 0x007F);
        }
        /* register CMN_DIAG_PLL0_TEST_MODE */
-       Afe_write(state, 0x01C4, 0x0020);
+       Afe_write(state, 0x01C4, 0x0022);
        /* register CMN_PSM_CLK_CTRL */
        Afe_write(state, 0x0061, 0x0016);