MLK-23190-3 ARM64: dts: imx8mp: add ecspi2 support
authorClark Wang <xiaoning.wang@nxp.com>
Fri, 3 Jan 2020 08:07:18 +0000 (16:07 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:23:22 +0000 (11:23 +0800)
Add ecspi2 node to support ECSPI on i.MX8mp.

Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
arch/arm64/boot/dts/freescale/imx8mp.dtsi

index 7eb1521..26aca7c 100644 (file)
        status = "okay";
 };
 
+&ecspi2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       spidev1: spi@0 {
+               reg = <0>;
+               compatible = "rohm,dh2228fv";
+               spi-max-frequency = <500000>;
+       };
+};
+
 &eqos {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_eqos>;
                >;
        };
 
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK           0x82
+                       MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI           0x82
+                       MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO           0x82
+               >;
+       };
+
+       pinctrl_ecspi2_cs: ecspi2cs {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13             0x40000
+               >;
+       };
+
        pinctrl_eqos: eqosgrp {
                fsl,pins = <
                        MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC             0x3
index 448ff98..06127d9 100644 (file)
                        ecspi1: spi@30820000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+                               compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
                                reg = <0x30820000 0x10000>;
                                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
                                         <&clk IMX8MP_CLK_ECSPI1_ROOT>;
                                clock-names = "ipg", "per";
+                               assigned-clock-rates = <80000000>;
+                               assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
                                dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
                                dma-names = "rx", "tx";
                                status = "disabled";
                        ecspi2: spi@30830000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+                               compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
                                reg = <0x30830000 0x10000>;
                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
                                         <&clk IMX8MP_CLK_ECSPI2_ROOT>;
                                clock-names = "ipg", "per";
+                               assigned-clock-rates = <80000000>;
+                               assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
                                dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
                                dma-names = "rx", "tx";
                                status = "disabled";
                        ecspi3: spi@30840000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+                               compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
                                reg = <0x30840000 0x10000>;
                                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
                                         <&clk IMX8MP_CLK_ECSPI3_ROOT>;
                                clock-names = "ipg", "per";
+                               assigned-clock-rates = <80000000>;
+                               assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
                                dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
                                dma-names = "rx", "tx";
                                status = "disabled";