pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ phy-reset-post-delay = <150>;
+ phy-reset-duration = <10>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
- ethphy0: ethernet-phy@1 {
+ ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
+ reg = <4>;
eee-broken-1000t;
};
};
status = "okay";
};
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- eee-broken-1000t;
- };
- };
-};
-
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-reset-post-delay = <150>;
+ phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
- ethphy1: ethernet-phy@1 {
+ ethphy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
+ reg = <4>;
eee-broken-1000t;
};
};
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19
>;
};
#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_FEC_MXC_PHYADDR 4
-#define DWC_NET_PHYADDR 1
+#define DWC_NET_PHYADDR 4
#define PHY_ANEG_TIMEOUT 20000