MLK-24752-1 arch: arm64: imx8m: add IR support

Add IR support for i.MX8MM/MN/MQ.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 05aa8da..ba16524 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -36,6 +36,13 @@
                #reset-cells = <0>;
        };
 
+       ir_recv: ir-receiver {
+               compatible = "gpio-ir-receiver";
+               gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ir_recv>;
+       };
+
        usdhc1_pwrseq: usdhc1_pwrseq {
                compatible = "mmc-pwrseq-simple";
                pinctrl-names = "default";
@@ -506,6 +513,12 @@
                >;
        };
 
+       pinctrl_ir_recv: ir-recv {
+               fsl,pins = <
+                       MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
+               >;
+       };
+
        pinctrl_fec1: fec1grp {
                fsl,pins = <
                        MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 698789b..7890607 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -41,6 +41,13 @@
                #reset-cells = <0>;
        };
 
+       ir_recv: ir-receiver {
+               compatible = "gpio-ir-receiver";
+               gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ir_recv>;
+       };
+
        resmem: reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -850,6 +857,12 @@
 
        };
 
+       pinctrl_ir_recv: ir-recv {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x4f
+               >;
+       };
+
        pinctrl_csi1_pwn: csi1_pwn_grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x19