MLK-14897-0: imx7d: dts: Add enet_axi and enet_phy clock parents and rates

Add clock parents and rates for enet_axi and enet_phy in dts via
the asigned-parents and assigned-rates attributes.
These were previously set in the ccm driver via set_parent/set_rate
calls but that has been removed in upstream linux.

Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 33c0303..f126906 100644 (file)
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -274,10 +274,15 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
        pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>;
-       assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
-                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
-       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-       assigned-clock-rates = <0>, <100000000>;
+       assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+                         <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+                         <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
        phy-mode = "rgmii";
        phy-handle = <&ethphy0>;
        fsl,magic-packet;
@@ -303,10 +308,15 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>;
        pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-       assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
-                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
-       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-       assigned-clock-rates = <0>, <100000000>;
+       assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+                         <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+                         <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+                         <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
        phy-mode = "rgmii";
        phy-handle = <&ethphy1>;
        fsl,magic-packet;