drm/amdgpu: Add replay counter defines to NBIO headers
authorKent Russell <kent.russell@amd.com>
Tue, 30 Apr 2019 10:42:24 +0000 (06:42 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 24 May 2019 17:20:48 +0000 (12:20 -0500)
Add the PCIE_RX_NUM_NACK and PCIE_RX_NUM_NACK_GENERATED values to the
NBIO SMN headers in preparation for exposing the number of PCIe replays
via sysfs

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h

index 8c75669..9470ec5 100644 (file)
@@ -54,5 +54,8 @@
 #define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
 #define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_6_1_SMN_HEADER
 
index 5563f07..caf5ffd 100644 (file)
@@ -51,4 +51,7 @@
 #define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
 #define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_7_0_SMN_HEADER
index c1457d8..4bcacf5 100644 (file)
@@ -50,4 +50,7 @@
 #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL            0x1118024c
 #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL            0x11180250
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_7_4_0_SMN_HEADER