MLK-19120-1 imx: hdp: Add AVPLL support for DisplayPort on iMX8QM

Add AVPLL support for DisplayPort on iMX8QM.
The AVPLL will be the default pixel clock source for DisplayPort.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

diff --git a/drivers/gpu/drm/imx/hdp/imx-hdp.c b/drivers/gpu/drm/imx/hdp/imx-hdp.c
index 5adac81..e0a2100 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/imx-hdp.c
+++ b/drivers/gpu/drm/imx/hdp/imx-hdp.c
@@ -293,7 +293,7 @@ int imx8qm_pixel_clock_enable(struct hdp_clks *clks)
 
        ret = clk_prepare_enable(clks->av_pll);
        if (ret < 0) {
-               dev_err(dev, "%s, pre clk pxl error\n", __func__);
+               dev_err(dev, "%s, pre av pll  error\n", __func__);
                return ret;
        }
 
@@ -336,8 +336,28 @@ void imx8qm_dp_pixel_clock_set_rate(struct hdp_clks *clks)
        struct imx_hdp *hdp = clks_to_imx_hdp(clks);
        unsigned int pclock = hdp->video.cur_mode.clock * 1000;
 
-       /* 24MHz for DP */
-       clk_set_rate(clks->av_pll, 24000000);
+       if (!hdp->is_digpll_dp_pclock) {
+               sc_err_t sci_err = 0;
+               sc_ipc_t ipc_handle = 0;
+               u32 mu_id;
+
+               sci_err = sc_ipc_getMuID(&mu_id);
+
+               if (sci_err != SC_ERR_NONE)
+                       pr_err("Failed to get MU ID (%d)\n", sci_err);
+               sci_err = sc_ipc_open(&ipc_handle, mu_id);
+
+               if (sci_err != SC_ERR_NONE)
+                       pr_err("Failed to open IPC (%d)\n", sci_err);
+
+               clk_set_rate(clks->av_pll, pclock);
+
+               /* Enable the 24MHz for HDP PHY */
+               sc_misc_set_control(ipc_handle, SC_R_HDMI, SC_C_MODE, 1);
+
+               sc_ipc_close(ipc_handle);
+       } else
+               clk_set_rate(clks->av_pll, 24000000);
 
        if (hdp->dual_mode == true) {
                clk_set_rate(clks->clk_pxl, pclock/2);
@@ -462,23 +482,33 @@ void imx8qm_ipg_clock_disable(struct hdp_clks *clks)
 
 void imx8qm_ipg_clock_set_rate(struct hdp_clks *clks)
 {
-       u32 clk_rate;
+       struct imx_hdp *hdp = clks_to_imx_hdp(clks);
+       u32 clk_rate, desired_rate;
+
+       if (hdp->is_digpll_dp_pclock)
+               desired_rate = PLL_1188MHZ;
+       else
+               desired_rate = PLL_675MHZ;
 
        /* hdmi/dp ipg/core clock */
        clk_rate = clk_get_rate(clks->dig_pll);
 
-       if (clk_rate != PLL_1188MHZ) {
-               pr_warn("%s, dig_pll was %u MHz, changing to 1188 MHz\n",
-                       __func__, clk_rate/1000000);
+       if (clk_rate != desired_rate) {
+               pr_warn("%s, dig_pll was %u MHz, changing to %u MHz\n",
+                       __func__, clk_rate/1000000,
+                       desired_rate/1000000);
        }
 
-       /* Force to 1188 MHz until we know better */
-       clk_set_rate(clks->dig_pll, PLL_1188MHZ);
-       clk_set_rate(clks->clk_core, PLL_1188MHZ/10);
-       clk_set_rate(clks->clk_ipg, PLL_1188MHZ/14);
-
-       /* Set Default av pll clock */
-       clk_set_rate(clks->av_pll, 24000000);
+       if (hdp->is_digpll_dp_pclock) {
+               clk_set_rate(clks->dig_pll,  desired_rate);
+               clk_set_rate(clks->clk_core, desired_rate/10);
+               clk_set_rate(clks->clk_ipg,  desired_rate/12);
+               clk_set_rate(clks->av_pll, 24000000);
+       } else {
+               clk_set_rate(clks->dig_pll,  desired_rate);
+               clk_set_rate(clks->clk_core, desired_rate/5);
+               clk_set_rate(clks->clk_ipg,  desired_rate/8);
+       }
 }
 
 static u8 imx_hdp_link_rate(struct drm_display_mode *mode)
@@ -1111,6 +1141,8 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master,
 
        hdp->is_cec = of_property_read_bool(pdev->dev.of_node, "fsl,cec");
 
+       hdp->is_digpll_dp_pclock = of_property_read_bool(pdev->dev.of_node, "fsl,use_digpll_pclock");
+
        hdp->is_edp = of_property_read_bool(pdev->dev.of_node, "fsl,edp");
 
        ret = of_property_read_u32(pdev->dev.of_node,

diff --git a/drivers/gpu/drm/imx/hdp/imx-hdp.h b/drivers/gpu/drm/imx/hdp/imx-hdp.h
index 69de718..1694530 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/imx-hdp.h
+++ b/drivers/gpu/drm/imx/hdp/imx-hdp.h
@@ -203,6 +203,7 @@ struct imx_hdp {
        u8 is_4kp60;
        u8 is_cec;
        u8 is_edp;
+       u8 is_digpll_dp_pclock;
        u8 audio_type;
        u32 lane_mapping;
        u32 edp_link_rate;