MLK-11414-3 ARM: dts: imx: apply ENET IRQ workaround for sabresd board
authorShawn Guo <shawn.guo@freescale.com>
Mon, 15 Sep 2014 03:32:40 +0000 (11:32 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 19:48:26 +0000 (14:48 -0500)
Cherry-pick below patch:

ENGR00317981 ARM: dts: imx: apply ENET IRQ workaround for sabresd board

This a forward porting of commit (ENGR00313685-15 ARM: dts: imx: apply
ENET IRQ workaround for sabresd board) from imx_3.10.y to imx_3.14.y.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6q-sabresd-enetirq.dts
arch/arm/boot/dts/imx6qdl-sabresd.dtsi

index 36a6e47..356dc96 100644 (file)
@@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6dl-tx6u-811x.dtb \
        imx6dl-tx6u-81xx-mb7.dtb \
        imx6dl-udoo.dtb \
+       imx6dl-sabresd-enetirq.dtb \
        imx6dl-wandboard.dtb \
        imx6dl-wandboard-revb1.dtb \
        imx6q-apalis-ixora.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts b/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts
new file mode 100644 (file)
index 0000000..b23d0eb
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dl-sabresd.dts"
+
+&fec {
+       pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
+       interrupts-extended = <&gpio1 6 0x04>, <&intc 0 119 0x04>;
+};
+
+&i2c3 {
+       status = "disabled";
+};
index 6dda35c..14b1cfa 100644 (file)
@@ -7,3 +7,12 @@
  */
 
 #include "imx6q-sabresd.dts"
+
+&fec {
+       pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
+       interrupts-extended = <&gpio1 6 0x04>, <&intc 0 119 0x04>;
+};
+
+&i2c3 {
+       status = "disabled";
+};
index 9a0194a..1b51574 100644 (file)
                        >;
                };
 
+               pinctrl_enet_irq: enetirqgrp {
+                       fsl,pins = <
+                               MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                       >;
+               };
+
                pinctrl_gpio_keys: gpio_keysgrp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0