ENGR00318895-11 mtd: fsl-quadspi: add DDR quad read support for Micron

Add DDR quad read opcode and LUT sequence for Micron N25Q256A.

Signed-off-by: Huang Shijie <b32955@freescale.com>
(cherry picked from commit dc2a7430557dd3e102b56fdd6b6d0fe3b1e3e461)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 1e5991f..6e881bd 100644 (file)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -417,6 +417,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
                        qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
                                    | LUT1(JMP_ON_CS, PAD1, 0),
                                    base + QUADSPI_LUT(lut_base + 2));
+               } else if (op == SPINOR_OP_READ_1_1_4_D) {
+                       /* read mode : 1-1-4, such as Micron N25Q256A. */
+                       qspi_writel(q, LUT0(CMD, PAD1, op)
+                                   | LUT1(ADDR_DDR, PAD1, addrlen),
+                                   base + QUADSPI_LUT(lut_base));
+
+                       qspi_writel(q, LUT0(DUMMY, PAD1, dm)
+                                   | LUT1(FSL_READ_DDR, PAD4, rxfifo),
+                                   base + QUADSPI_LUT(lut_base + 1));
+
+                       qspi_writel(q, LUT0(JMP_ON_CS, PAD1, 0),
+                                   base + QUADSPI_LUT(lut_base + 2));
                } else {
                        dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
                }
@@ -490,6 +502,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 {
        switch (cmd) {
+       case SPINOR_OP_READ_1_1_4_D:
        case SPINOR_OP_READ_1_4_4_D:
        case SPINOR_OP_READ4_1_4_4_D:
        case SPINOR_OP_READ4_1_1_4: