scsi: hisi_sas: Set the BIST init value before enabling BIST
authorXiang Chen <chenxiang66@hisilicon.com>
Thu, 24 Oct 2019 14:08:09 +0000 (22:08 +0800)
committerMartin K. Petersen <martin.petersen@oracle.com>
Fri, 25 Oct 2019 01:31:13 +0000 (21:31 -0400)
If set the BIST init value after enabling BIST, there may be still some few
error bits. According to the process, need to set the BIST init value
before enabling BIST.

Fixes: 97b151e75861 ("scsi: hisi_sas: Add BIST support for phy loopback")
Link: https://lore.kernel.org/r/1571926105-74636-3-git-send-email-john.garry@huawei.com
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

index cb8d087..cc59493 100644 (file)
@@ -3022,11 +3022,6 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
                hisi_sas_phy_write32(hisi_hba, phy_id,
                                     SAS_PHY_BIST_CTRL, reg_val);
 
-               mdelay(100);
-               reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
-               hisi_sas_phy_write32(hisi_hba, phy_id,
-                                    SAS_PHY_BIST_CTRL, reg_val);
-
                /* set the bist init value */
                hisi_sas_phy_write32(hisi_hba, phy_id,
                                     SAS_PHY_BIST_CODE,
@@ -3035,6 +3030,11 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
                                     SAS_PHY_BIST_CODE1,
                                     SAS_PHY_BIST_CODE1_INIT);
 
+               mdelay(100);
+               reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
+               hisi_sas_phy_write32(hisi_hba, phy_id,
+                                    SAS_PHY_BIST_CTRL, reg_val);
+
                /* clear error bit */
                mdelay(100);
                hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);