MLK-22748 imx8mn: Fix flexspi flash SCLK violation

Current flexspi driver enables the Quad DTR read, so the measured
100Mhz SCLK is actually for DTR mode not SDR. However, according to
MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and
max SDR at 166Mhz. It means current clock setting violate the flash
spec. So change back the flexspi clock to align with imx8mm.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 3bf41bae974003550b70ea1a8b44ccb3117d818f)
(cherry picked from commit 4a369b527c3842751a4edf0171562a0e40c331ba)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 5670fd2..33303f2 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -728,14 +728,7 @@ int set_clk_qspi(void)
         * sys pll1 100M
         */
        clock_enable(CCGR_QSPI, 0);
-
-       if (is_imx8mn()) {
-               clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1)  | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
-       } else {
-               clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(7));
-       }
+       clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7));
        clock_enable(CCGR_QSPI, 1);
 
        return 0;